scsi: arcmsr: Adjust whitespace
Adjust tabs and whitespace. Signed-off-by: Ching Huang <ching2048@areca.com.tw> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Ching Huang
Martin K. Petersen
parent
ea331f30ec
commit
a3de4b58bc
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@ -50,35 +50,35 @@ struct device_attribute;
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#define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
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#define ARCMSR_MIN_OUTSTANDING_CMD 32
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#define ARCMSR_DRIVER_VERSION "v1.30.00.22-20151126"
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_MAX_XFER_SECTORS 512
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#define ARCMSR_MAX_XFER_SECTORS_B 4096
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#define ARCMSR_MAX_XFER_SECTORS_C 304
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#define ARCMSR_MAX_TARGETID 17
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#define ARCMSR_MAX_TARGETLUN 8
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_MAX_XFER_SECTORS 512
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#define ARCMSR_MAX_XFER_SECTORS_B 4096
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#define ARCMSR_MAX_XFER_SECTORS_C 304
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#define ARCMSR_MAX_TARGETID 17
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#define ARCMSR_MAX_TARGETLUN 8
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#define ARCMSR_MAX_CMD_PERLUN 128
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#define ARCMSR_DEFAULT_CMD_PERLUN 32
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#define ARCMSR_MIN_CMD_PERLUN 1
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#define ARCMSR_MAX_QBUFFER 4096
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#define ARCMSR_DEFAULT_SG_ENTRIES 38
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#define ARCMSR_MAX_HBB_POSTQUEUE 264
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#define ARCMSR_MAX_QBUFFER 4096
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#define ARCMSR_DEFAULT_SG_ENTRIES 38
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#define ARCMSR_MAX_HBB_POSTQUEUE 264
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#define ARCMSR_MAX_ARC1214_POSTQUEUE 256
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#define ARCMSR_MAX_ARC1214_DONEQUEUE 257
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#define ARCMSR_MAX_HBE_DONEQUEUE 512
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#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
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#define ARCMSR_CDB_SG_PAGE_LENGTH 256
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#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
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#define ARCMSR_CDB_SG_PAGE_LENGTH 256
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#define ARCMST_NUM_MSIX_VECTORS 4
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#ifndef PCI_DEVICE_ID_ARECA_1880
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#define PCI_DEVICE_ID_ARECA_1880 0x1880
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#endif
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#define PCI_DEVICE_ID_ARECA_1880 0x1880
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#endif
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#ifndef PCI_DEVICE_ID_ARECA_1214
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#define PCI_DEVICE_ID_ARECA_1214 0x1214
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#define PCI_DEVICE_ID_ARECA_1214 0x1214
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#endif
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#ifndef PCI_DEVICE_ID_ARECA_1203
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#define PCI_DEVICE_ID_ARECA_1203 0x1203
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#define PCI_DEVICE_ID_ARECA_1203 0x1203
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#endif
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#ifndef PCI_DEVICE_ID_ARECA_1884
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#define PCI_DEVICE_ID_ARECA_1884 0x1884
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#define PCI_DEVICE_ID_ARECA_1884 0x1884
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#endif
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#define ARCMSR_HOURS (1000 * 60 * 60 * 4)
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#define ARCMSR_MINUTES (1000 * 60 * 60)
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@ -87,15 +87,15 @@ struct device_attribute;
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**
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**********************************************************************************
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*/
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#define ARC_SUCCESS 0
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#define ARC_FAILURE 1
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#define ARC_SUCCESS 0
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#define ARC_FAILURE 1
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/*
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*******************************************************************************
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** split 64bits dma addressing
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*******************************************************************************
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*/
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#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
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#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
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#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
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#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
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/*
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*******************************************************************************
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** MESSAGE CONTROL CODE
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@ -135,7 +135,7 @@ struct CMD_MESSAGE_FIELD
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#define FUNCTION_SAY_HELLO 0x0807
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#define FUNCTION_SAY_GOODBYE 0x0808
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#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
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#define FUNCTION_GET_FIRMWARE_STATUS 0x080A
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#define FUNCTION_GET_FIRMWARE_STATUS 0x080A
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#define FUNCTION_HARDWARE_RESET 0x080B
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/* ARECA IO CONTROL CODE*/
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#define ARCMSR_MESSAGE_READ_RQBUFFER \
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@ -166,18 +166,18 @@ struct CMD_MESSAGE_FIELD
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** structure for holding DMA address data
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*************************************************************
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*/
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#define IS_DMA64 (sizeof(dma_addr_t) == 8)
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#define IS_SG64_ADDR 0x01000000 /* bit24 */
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#define IS_DMA64 (sizeof(dma_addr_t) == 8)
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#define IS_SG64_ADDR 0x01000000 /* bit24 */
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struct SG32ENTRY
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{
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__le32 length;
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__le32 address;
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__le32 length;
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__le32 address;
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}__attribute__ ((packed));
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struct SG64ENTRY
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{
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__le32 length;
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__le32 address;
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__le32 addresshigh;
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__le32 length;
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__le32 address;
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__le32 addresshigh;
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}__attribute__ ((packed));
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/*
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********************************************************************
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@ -196,50 +196,50 @@ struct QBUFFER
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*/
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struct FIRMWARE_INFO
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{
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uint32_t signature; /*0, 00-03*/
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uint32_t request_len; /*1, 04-07*/
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uint32_t numbers_queue; /*2, 08-11*/
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uint32_t sdram_size; /*3, 12-15*/
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uint32_t ide_channels; /*4, 16-19*/
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char vendor[40]; /*5, 20-59*/
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char model[8]; /*15, 60-67*/
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char firmware_ver[16]; /*17, 68-83*/
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char device_map[16]; /*21, 84-99*/
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uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
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uint8_t cfgSerial[16]; /*26,104-119*/
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uint32_t cfgPicStatus; /*30,120-123*/
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uint32_t signature; /*0, 00-03*/
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uint32_t request_len; /*1, 04-07*/
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uint32_t numbers_queue; /*2, 08-11*/
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uint32_t sdram_size; /*3, 12-15*/
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uint32_t ide_channels; /*4, 16-19*/
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char vendor[40]; /*5, 20-59*/
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char model[8]; /*15, 60-67*/
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char firmware_ver[16]; /*17, 68-83*/
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char device_map[16]; /*21, 84-99*/
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uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
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uint8_t cfgSerial[16]; /*26,104-119*/
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uint32_t cfgPicStatus; /*30,120-123*/
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};
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/* signature of set and get firmware config */
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#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
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#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
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/* message code of inbound message register */
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#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
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#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
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#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
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#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
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#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
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#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
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#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
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#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
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#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
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#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
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#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
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#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
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#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
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#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
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#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
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#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
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#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
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#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
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/* doorbell interrupt generator */
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#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
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#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
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#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
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#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
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#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
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#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
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#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
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#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
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/* ccb areca cdb flag */
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#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
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#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
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#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
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#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
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/* outbound firmware ok */
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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/* ARC-1680 Bus Reset*/
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#define ARCMSR_ARC1680_BUS_RESET 0x00000003
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#define ARCMSR_ARC1680_BUS_RESET 0x00000003
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/* ARC-1880 Bus Reset*/
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#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
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#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
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#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
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#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
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/*
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************************************************************************
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@ -282,10 +282,10 @@ struct FIRMWARE_INFO
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#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
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/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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#define ARCMSR_MESSAGE_START_BGRB 0x00060008
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#define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
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#define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008
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#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
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#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
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#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
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#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
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/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
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#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
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/* ioctl transfer */
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@ -294,7 +294,7 @@ struct FIRMWARE_INFO
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#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
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#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
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#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
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#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
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#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
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/* data tunnel buffer between user space program and its firmware */
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/* user space data to iop 128bytes */
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@ -319,12 +319,12 @@ struct FIRMWARE_INFO
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#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
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#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
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/* Host Interrupt Status */
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#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
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#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
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/*
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** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
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** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
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*/
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#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
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#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
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/*
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** Set if Outbound Doorbell register bits 30:1 have a non-zero
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** value. This bit clears only when Outbound Doorbell bits
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@ -337,7 +337,7 @@ struct FIRMWARE_INFO
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** Register (FIFO) is not empty. It clears when the Outbound
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** Post List FIFO is empty.
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*/
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#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
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#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
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/*
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** This bit indicates a SAS interrupt from a source external to
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** the PCIe core. This bit is not maskable.
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@ -346,17 +346,17 @@ struct FIRMWARE_INFO
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#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
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#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
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/*inbound message 0 ready*/
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#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
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#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
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/*more than 12 request completed in a time*/
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#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
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#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
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/*outbound DATA WRITE isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
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#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
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#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
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/*outbound DATA READ isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
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#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
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/*outbound message 0 ready*/
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#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
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#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
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/*outbound message cmd isr door bell clear*/
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#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
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/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
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@ -443,13 +443,13 @@ struct FIRMWARE_INFO
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*/
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struct ARCMSR_CDB
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{
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uint8_t Bus;
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uint8_t TargetID;
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uint8_t LUN;
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uint8_t Function;
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uint8_t CdbLength;
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uint8_t sgcount;
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uint8_t Flags;
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uint8_t Bus;
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uint8_t TargetID;
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uint8_t LUN;
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uint8_t Function;
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uint8_t CdbLength;
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uint8_t sgcount;
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uint8_t Flags;
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#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
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#define ARCMSR_CDB_FLAG_BIOS 0x02
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#define ARCMSR_CDB_FLAG_WRITE 0x04
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@ -457,21 +457,21 @@ struct ARCMSR_CDB
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#define ARCMSR_CDB_FLAG_HEADQ 0x08
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#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
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uint8_t msgPages;
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uint32_t msgContext;
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uint32_t DataLength;
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uint8_t Cdb[16];
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uint8_t DeviceStatus;
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uint8_t msgPages;
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uint32_t msgContext;
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uint32_t DataLength;
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uint8_t Cdb[16];
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uint8_t DeviceStatus;
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#define ARCMSR_DEV_CHECK_CONDITION 0x02
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#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
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#define ARCMSR_DEV_ABORTED 0xF1
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#define ARCMSR_DEV_INIT_FAIL 0xF2
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uint8_t SenseData[15];
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uint8_t SenseData[15];
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union
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{
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struct SG32ENTRY sg32entry[1];
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struct SG64ENTRY sg64entry[1];
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struct SG32ENTRY sg32entry[1];
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struct SG64ENTRY sg64entry[1];
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} u;
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};
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/*
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@ -511,13 +511,13 @@ struct MessageUnit_B
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uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
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uint32_t postq_index;
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uint32_t doneq_index;
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uint32_t __iomem *drv2iop_doorbell;
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uint32_t __iomem *drv2iop_doorbell_mask;
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uint32_t __iomem *iop2drv_doorbell;
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uint32_t __iomem *iop2drv_doorbell_mask;
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uint32_t __iomem *message_rwbuffer;
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uint32_t __iomem *message_wbuffer;
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uint32_t __iomem *message_rbuffer;
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uint32_t __iomem *drv2iop_doorbell;
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uint32_t __iomem *drv2iop_doorbell_mask;
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uint32_t __iomem *iop2drv_doorbell;
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uint32_t __iomem *iop2drv_doorbell_mask;
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uint32_t __iomem *message_rwbuffer;
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uint32_t __iomem *message_wbuffer;
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uint32_t __iomem *message_rbuffer;
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};
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/*
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*********************************************************************
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@ -537,7 +537,7 @@ struct MessageUnit_C{
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uint32_t diagnostic_rw_data; /*0024 0027*/
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uint32_t diagnostic_rw_address_low; /*0028 002B*/
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uint32_t diagnostic_rw_address_high; /*002C 002F*/
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uint32_t host_int_status; /*0030 0033*/
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uint32_t host_int_status; /*0030 0033*/
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uint32_t host_int_mask; /*0034 0037*/
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uint32_t dcr_data; /*0038 003B*/
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uint32_t dcr_address; /*003C 003F*/
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@ -549,12 +549,12 @@ struct MessageUnit_C{
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uint32_t iop_int_mask; /*0054 0057*/
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uint32_t iop_inbound_queue_port; /*0058 005B*/
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uint32_t iop_outbound_queue_port; /*005C 005F*/
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uint32_t inbound_free_list_index; /*0060 0063*/
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uint32_t inbound_post_list_index; /*0064 0067*/
|
||||
uint32_t outbound_free_list_index; /*0068 006B*/
|
||||
uint32_t outbound_post_list_index; /*006C 006F*/
|
||||
uint32_t inbound_free_list_index; /*0060 0063*/
|
||||
uint32_t inbound_post_list_index; /*0064 0067*/
|
||||
uint32_t outbound_free_list_index; /*0068 006B*/
|
||||
uint32_t outbound_post_list_index; /*006C 006F*/
|
||||
uint32_t inbound_doorbell_clear; /*0070 0073*/
|
||||
uint32_t i2o_message_unit_control; /*0074 0077*/
|
||||
uint32_t i2o_message_unit_control; /*0074 0077*/
|
||||
uint32_t last_used_message_source_address_low; /*0078 007B*/
|
||||
uint32_t last_used_message_source_address_high; /*007C 007F*/
|
||||
uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
|
||||
|
|
@ -562,7 +562,7 @@ struct MessageUnit_C{
|
|||
uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
|
||||
uint32_t utility_A_int_counter_timer; /*0098 009B*/
|
||||
uint32_t outbound_doorbell; /*009C 009F*/
|
||||
uint32_t outbound_doorbell_clear; /*00A0 00A3*/
|
||||
uint32_t outbound_doorbell_clear; /*00A0 00A3*/
|
||||
uint32_t message_source_address_index; /*00A4 00A7*/
|
||||
uint32_t message_done_queue_index; /*00A8 00AB*/
|
||||
uint32_t reserved0; /*00AC 00AF*/
|
||||
|
|
@ -584,10 +584,10 @@ struct MessageUnit_C{
|
|||
uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
|
||||
uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
|
||||
uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
|
||||
uint32_t host_diagnostic; /*00F8 00FB*/
|
||||
uint32_t host_diagnostic; /*00F8 00FB*/
|
||||
uint32_t write_sequence; /*00FC 00FF*/
|
||||
uint32_t reserved1[34]; /*0100 0187*/
|
||||
uint32_t reserved2[1950]; /*0188 1FFF*/
|
||||
uint32_t reserved2[1950]; /*0188 1FFF*/
|
||||
uint32_t message_wbuffer[32]; /*2000 207F*/
|
||||
uint32_t reserved3[32]; /*2080 20FF*/
|
||||
uint32_t message_rbuffer[32]; /*2100 217F*/
|
||||
|
|
@ -733,26 +733,26 @@ typedef struct deliver_completeQ {
|
|||
*/
|
||||
struct AdapterControlBlock
|
||||
{
|
||||
uint32_t adapter_type; /* adapter A,B..... */
|
||||
#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
|
||||
#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
|
||||
#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
|
||||
#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
|
||||
#define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
|
||||
u32 roundup_ccbsize;
|
||||
struct pci_dev * pdev;
|
||||
struct Scsi_Host * host;
|
||||
unsigned long vir2phy_offset;
|
||||
uint32_t adapter_type; /* adapter A,B..... */
|
||||
#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */
|
||||
#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */
|
||||
#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
|
||||
#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
|
||||
#define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
|
||||
u32 roundup_ccbsize;
|
||||
struct pci_dev * pdev;
|
||||
struct Scsi_Host * host;
|
||||
unsigned long vir2phy_offset;
|
||||
/* Offset is used in making arc cdb physical to virtual calculations */
|
||||
uint32_t outbound_int_enable;
|
||||
uint32_t cdb_phyaddr_hi32;
|
||||
uint32_t reg_mu_acc_handle0;
|
||||
spinlock_t eh_lock;
|
||||
spinlock_t ccblist_lock;
|
||||
spinlock_t postq_lock;
|
||||
spinlock_t doneq_lock;
|
||||
spinlock_t rqbuffer_lock;
|
||||
spinlock_t wqbuffer_lock;
|
||||
uint32_t outbound_int_enable;
|
||||
uint32_t cdb_phyaddr_hi32;
|
||||
uint32_t reg_mu_acc_handle0;
|
||||
spinlock_t eh_lock;
|
||||
spinlock_t ccblist_lock;
|
||||
spinlock_t postq_lock;
|
||||
spinlock_t doneq_lock;
|
||||
spinlock_t rqbuffer_lock;
|
||||
spinlock_t wqbuffer_lock;
|
||||
union {
|
||||
struct MessageUnit_A __iomem *pmuA;
|
||||
struct MessageUnit_B *pmuB;
|
||||
|
|
@ -761,84 +761,84 @@ struct AdapterControlBlock
|
|||
struct MessageUnit_E __iomem *pmuE;
|
||||
};
|
||||
/* message unit ATU inbound base address0 */
|
||||
void __iomem *mem_base0;
|
||||
void __iomem *mem_base1;
|
||||
uint32_t acb_flags;
|
||||
void __iomem *mem_base0;
|
||||
void __iomem *mem_base1;
|
||||
uint32_t acb_flags;
|
||||
u16 dev_id;
|
||||
uint8_t adapter_index;
|
||||
#define ACB_F_SCSISTOPADAPTER 0x0001
|
||||
#define ACB_F_MSG_STOP_BGRB 0x0002
|
||||
/* stop RAID background rebuild */
|
||||
#define ACB_F_MSG_START_BGRB 0x0004
|
||||
/* stop RAID background rebuild */
|
||||
#define ACB_F_IOPDATA_OVERFLOW 0x0008
|
||||
/* iop message data rqbuffer overflow */
|
||||
#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
|
||||
/* message clear wqbuffer */
|
||||
#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
|
||||
/* message clear rqbuffer */
|
||||
#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
|
||||
#define ACB_F_BUS_RESET 0x0080
|
||||
#define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
|
||||
uint8_t adapter_index;
|
||||
#define ACB_F_SCSISTOPADAPTER 0x0001
|
||||
#define ACB_F_MSG_STOP_BGRB 0x0002
|
||||
/* stop RAID background rebuild */
|
||||
#define ACB_F_MSG_START_BGRB 0x0004
|
||||
/* stop RAID background rebuild */
|
||||
#define ACB_F_IOPDATA_OVERFLOW 0x0008
|
||||
/* iop message data rqbuffer overflow */
|
||||
#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
|
||||
/* message clear wqbuffer */
|
||||
#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
|
||||
/* message clear rqbuffer */
|
||||
#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
|
||||
#define ACB_F_BUS_RESET 0x0080
|
||||
#define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
|
||||
|
||||
#define ACB_F_IOP_INITED 0x0100
|
||||
/* iop init */
|
||||
#define ACB_F_ABORT 0x0200
|
||||
#define ACB_F_FIRMWARE_TRAP 0x0400
|
||||
#define ACB_F_MSG_GET_CONFIG 0x1000
|
||||
struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
|
||||
#define ACB_F_IOP_INITED 0x0100
|
||||
/* iop init */
|
||||
#define ACB_F_ABORT 0x0200
|
||||
#define ACB_F_FIRMWARE_TRAP 0x0400
|
||||
#define ACB_F_MSG_GET_CONFIG 0x1000
|
||||
struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
|
||||
/* used for memory free */
|
||||
struct list_head ccb_free_list;
|
||||
struct list_head ccb_free_list;
|
||||
/* head of free ccb list */
|
||||
|
||||
atomic_t ccboutstandingcount;
|
||||
atomic_t ccboutstandingcount;
|
||||
/*The present outstanding command number that in the IOP that
|
||||
waiting for being handled by FW*/
|
||||
|
||||
void * dma_coherent;
|
||||
void * dma_coherent;
|
||||
/* dma_coherent used for memory free */
|
||||
dma_addr_t dma_coherent_handle;
|
||||
dma_addr_t dma_coherent_handle;
|
||||
/* dma_coherent_handle used for memory free */
|
||||
dma_addr_t dma_coherent_handle2;
|
||||
void *dma_coherent2;
|
||||
unsigned int uncache_size;
|
||||
uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
|
||||
dma_addr_t dma_coherent_handle2;
|
||||
void *dma_coherent2;
|
||||
unsigned int uncache_size;
|
||||
uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
|
||||
/* data collection buffer for read from 80331 */
|
||||
int32_t rqbuf_getIndex;
|
||||
int32_t rqbuf_getIndex;
|
||||
/* first of read buffer */
|
||||
int32_t rqbuf_putIndex;
|
||||
int32_t rqbuf_putIndex;
|
||||
/* last of read buffer */
|
||||
uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
|
||||
uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
|
||||
/* data collection buffer for write to 80331 */
|
||||
int32_t wqbuf_getIndex;
|
||||
int32_t wqbuf_getIndex;
|
||||
/* first of write buffer */
|
||||
int32_t wqbuf_putIndex;
|
||||
int32_t wqbuf_putIndex;
|
||||
/* last of write buffer */
|
||||
uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
|
||||
uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
|
||||
/* id0 ..... id15, lun0...lun7 */
|
||||
#define ARECA_RAID_GONE 0x55
|
||||
#define ARECA_RAID_GOOD 0xaa
|
||||
uint32_t num_resets;
|
||||
uint32_t num_aborts;
|
||||
uint32_t signature;
|
||||
uint32_t firm_request_len;
|
||||
uint32_t firm_numbers_queue;
|
||||
uint32_t firm_sdram_size;
|
||||
uint32_t firm_hd_channels;
|
||||
uint32_t firm_cfg_version;
|
||||
#define ARECA_RAID_GONE 0x55
|
||||
#define ARECA_RAID_GOOD 0xaa
|
||||
uint32_t num_resets;
|
||||
uint32_t num_aborts;
|
||||
uint32_t signature;
|
||||
uint32_t firm_request_len;
|
||||
uint32_t firm_numbers_queue;
|
||||
uint32_t firm_sdram_size;
|
||||
uint32_t firm_hd_channels;
|
||||
uint32_t firm_cfg_version;
|
||||
char firm_model[12];
|
||||
char firm_version[20];
|
||||
char device_map[20]; /*21,84-99*/
|
||||
struct work_struct arcmsr_do_message_isr_bh;
|
||||
struct timer_list eternal_timer;
|
||||
struct work_struct arcmsr_do_message_isr_bh;
|
||||
struct timer_list eternal_timer;
|
||||
unsigned short fw_flag;
|
||||
#define FW_NORMAL 0x0000
|
||||
#define FW_BOG 0x0001
|
||||
#define FW_DEADLOCK 0x0010
|
||||
atomic_t rq_map_token;
|
||||
atomic_t ante_token_value;
|
||||
uint32_t maxOutstanding;
|
||||
int vector_count;
|
||||
#define FW_NORMAL 0x0000
|
||||
#define FW_BOG 0x0001
|
||||
#define FW_DEADLOCK 0x0010
|
||||
atomic_t rq_map_token;
|
||||
atomic_t ante_token_value;
|
||||
uint32_t maxOutstanding;
|
||||
int vector_count;
|
||||
uint32_t maxFreeCCB;
|
||||
struct timer_list refresh_timer;
|
||||
uint32_t doneq_index;
|
||||
|
|
@ -856,30 +856,30 @@ struct AdapterControlBlock
|
|||
*/
|
||||
struct CommandControlBlock{
|
||||
/*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
|
||||
struct list_head list; /*x32: 8byte, x64: 16byte*/
|
||||
struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
|
||||
struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
|
||||
uint32_t cdb_phyaddr; /*x32: 4byte, x64: 4byte*/
|
||||
uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
|
||||
uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
|
||||
#define CCB_FLAG_READ 0x0000
|
||||
#define CCB_FLAG_WRITE 0x0001
|
||||
#define CCB_FLAG_ERROR 0x0002
|
||||
#define CCB_FLAG_FLUSHCACHE 0x0004
|
||||
#define CCB_FLAG_MASTER_ABORTED 0x0008
|
||||
uint16_t startdone; /*x32:2byte,x32:2byte*/
|
||||
#define ARCMSR_CCB_DONE 0x0000
|
||||
#define ARCMSR_CCB_START 0x55AA
|
||||
#define ARCMSR_CCB_ABORTED 0xAA55
|
||||
#define ARCMSR_CCB_ILLEGAL 0xFFFF
|
||||
struct list_head list; /*x32: 8byte, x64: 16byte*/
|
||||
struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
|
||||
struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
|
||||
uint32_t cdb_phyaddr; /*x32: 4byte, x64: 4byte*/
|
||||
uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
|
||||
uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
|
||||
#define CCB_FLAG_READ 0x0000
|
||||
#define CCB_FLAG_WRITE 0x0001
|
||||
#define CCB_FLAG_ERROR 0x0002
|
||||
#define CCB_FLAG_FLUSHCACHE 0x0004
|
||||
#define CCB_FLAG_MASTER_ABORTED 0x0008
|
||||
uint16_t startdone; /*x32:2byte,x32:2byte*/
|
||||
#define ARCMSR_CCB_DONE 0x0000
|
||||
#define ARCMSR_CCB_START 0x55AA
|
||||
#define ARCMSR_CCB_ABORTED 0xAA55
|
||||
#define ARCMSR_CCB_ILLEGAL 0xFFFF
|
||||
uint32_t smid;
|
||||
#if BITS_PER_LONG == 64
|
||||
#if BITS_PER_LONG == 64
|
||||
/* ======================512+64 bytes======================== */
|
||||
uint32_t reserved[4]; /*16 byte*/
|
||||
#else
|
||||
uint32_t reserved[4]; /*16 byte*/
|
||||
#else
|
||||
/* ======================512+32 bytes======================== */
|
||||
// uint32_t reserved; /*4 byte*/
|
||||
#endif
|
||||
// uint32_t reserved; /*4 byte*/
|
||||
#endif
|
||||
/* ======================================================= */
|
||||
struct ARCMSR_CDB arcmsr_cdb;
|
||||
};
|
||||
|
|
@ -913,13 +913,13 @@ struct SENSE_DATA
|
|||
** Outbound Interrupt Status Register - OISR
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
|
||||
#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
|
||||
#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
|
||||
#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
|
||||
#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
|
||||
#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
|
||||
#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
|
||||
#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
|
||||
#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
|
||||
#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
|
||||
(ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
|
||||
|ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
|
||||
|ARCMSR_MU_OUTBOUND_DOORBELL_INT \
|
||||
|
|
@ -930,13 +930,13 @@ struct SENSE_DATA
|
|||
** Outbound Interrupt Mask Register - OIMR
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
|
||||
#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
|
||||
#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
|
||||
#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
|
||||
#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
|
||||
#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
|
||||
#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
|
||||
#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
|
||||
#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
|
||||
#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
|
||||
#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
|
||||
|
||||
extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
|
||||
extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
|
||||
|
|
|
|||
|
|
@ -142,14 +142,14 @@ static struct scsi_host_template arcmsr_scsi_host_template = {
|
|||
.name = "Areca SAS/SATA RAID driver",
|
||||
.info = arcmsr_info,
|
||||
.queuecommand = arcmsr_queue_command,
|
||||
.eh_abort_handler = arcmsr_abort,
|
||||
.eh_abort_handler = arcmsr_abort,
|
||||
.eh_bus_reset_handler = arcmsr_bus_reset,
|
||||
.bios_param = arcmsr_bios_param,
|
||||
.change_queue_depth = arcmsr_adjust_disk_queue_depth,
|
||||
.can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
|
||||
.this_id = ARCMSR_SCSI_INITIATOR_ID,
|
||||
.sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
|
||||
.max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
|
||||
.this_id = ARCMSR_SCSI_INITIATOR_ID,
|
||||
.sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
|
||||
.max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
|
||||
.cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.shost_attrs = arcmsr_host_attrs,
|
||||
|
|
@ -207,7 +207,7 @@ MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
|
|||
|
||||
static struct pci_driver arcmsr_pci_driver = {
|
||||
.name = "arcmsr",
|
||||
.id_table = arcmsr_device_id_table,
|
||||
.id_table = arcmsr_device_id_table,
|
||||
.probe = arcmsr_probe,
|
||||
.remove = arcmsr_remove,
|
||||
.suspend = arcmsr_suspend,
|
||||
|
|
|
|||
Loading…
Reference in New Issue