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m68knommu: remove unecessary interrupt level setting in ColdFire 520x setup 

The new code for the interrupt controller in the ColdFire 520x takes
care of all the interrupt controller setup. No manual config of the
level registers (ICR) is required by the  platform device setup code.
So remove it.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2009-05-06 10:14:04 +10:00
parent de4cbfb599
commit a3d9bf1dfd
1 changed files with 0 additions and 9 deletions
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9
arch/m68knommu/platform/520x/config.c
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@ -81,15 +81,11 @@ static struct platform_device *m520x_devices[] __initdata = {
/***************************************************************************/
#define INTC0 (MCF_MBAR + MCFICM_INTC0)
static void __init m520x_uart_init_line(int line, int irq)
{
u16 par;
u8 par2;
writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
switch (line) {
case 0:
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
@ -128,11 +124,6 @@ static void __init m520x_fec_init(void)
{
u8 v;
/* Unmask FEC interrupts at ColdFire interrupt controller */
writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
/* Set multi-function pins to ethernet mode */
v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);