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staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports' 

Function 'mt7621_pcie_enable_ports' call 'mt7621_pcie_enable_port'
for each available pcie port. Instead of having two for loops
there just move needed initialization. There is one setting
that can be removed which is the set for 'PCI_COMMAND_MASTER'
bit. Pci drivers are in charge of set that bit if is really
needed and should be not a mission of the controller to do that.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos 2021-06-07 14:01:48 +02:00 committed by Greg Kroah-Hartman
parent 6771fb0b94
commit a3bb1d050e
1 changed files with 8 additions and 16 deletions
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24
drivers/staging/mt7621-pci/pci-mt7621.c
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@ -499,15 +499,18 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
/* configure class code and revision ID */
pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
offset + RALINK_PCI_CLASS);
/* configure RC FTS number to 250 when it leaves L0s */
val = read_config(pcie, slot, PCIE_FTS_NUM);
val &= ~PCIE_FTS_NUM_MASK;
val |= PCIE_FTS_NUM_L0(0x50);
write_config(pcie, slot, PCIE_FTS_NUM, val);
}
static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
struct mt7621_pcie_port *port;
u8 num_slots_enabled = 0;
u32 slot;
u32 val;
int err;
/* Setup MEMWIN and IOWIN */
@ -518,27 +521,16 @@ static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
if (port->enabled) {
err = clk_prepare_enable(port->clk);
if (err) {
dev_err(dev, "enabling clk pcie%d\n", slot);
dev_err(dev, "enabling clk pcie%d\n",
port->slot);
return err;
}
mt7621_pcie_enable_port(port);
dev_info(dev, "PCIE%d enabled\n", port->slot);
num_slots_enabled++;
}
}
for (slot = 0; slot < num_slots_enabled; slot++) {
val = read_config(pcie, slot, PCI_COMMAND);
val |= PCI_COMMAND_MASTER;
write_config(pcie, slot, PCI_COMMAND, val);
/* configure RC FTS number to 250 when it leaves L0s */
val = read_config(pcie, slot, PCIE_FTS_NUM);
val &= ~PCIE_FTS_NUM_MASK;
val |= PCIE_FTS_NUM_L0(0x50);
write_config(pcie, slot, PCIE_FTS_NUM, val);
}
return 0;
}