CRIS: Machine dependent dma.h
Move the old one to mach-fs and replace with a new one that only include the correct one for the machine architecture. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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Jesper Nilsson
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#ifndef _ASM_ARCH_CRIS_DMA_H
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#define _ASM_ARCH_CRIS_DMA_H
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/* Defines for using and allocating dma channels. */
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#define MAX_DMA_CHANNELS 10
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#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */
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#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */
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#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */
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#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */
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#define ATA_TX_DMA_NBR 2 /* ATA interface out. */
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#define ATA_RX_DMA_NBR 3 /* ATA interface in. */
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#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */
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#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */
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#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */
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#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */
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#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
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#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
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#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */
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#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */
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#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */
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#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */
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#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */
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#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */
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#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */
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#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */
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#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */
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#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */
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#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */
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#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */
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#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */
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#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */
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#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */
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#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */
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enum dma_owner
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{
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dma_eth0,
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dma_eth1,
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dma_iop0,
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dma_iop1,
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dma_ser0,
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dma_ser1,
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dma_ser2,
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dma_ser3,
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dma_sser0,
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dma_sser1,
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dma_ata,
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dma_strp,
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dma_ext0,
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dma_ext1,
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dma_ext2,
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dma_ext3
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};
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int crisv32_request_dma(unsigned int dmanr, const char * device_id,
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unsigned options, unsigned bandwidth, enum dma_owner owner);
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void crisv32_free_dma(unsigned int dmanr);
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/* Masks used by crisv32_request_dma options: */
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#define DMA_VERBOSE_ON_ERROR 1
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#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
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#define DMA_INT_MEM 4
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#endif /* _ASM_ARCH_CRIS_DMA_H */
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#include "mach/dma.h"
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#ifndef _ASM_ARCH_CRIS_DMA_H
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#define _ASM_ARCH_CRIS_DMA_H
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/* Defines for using and allocating dma channels. */
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#define MAX_DMA_CHANNELS 10
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#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */
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#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */
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#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */
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#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */
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#define ATA_TX_DMA_NBR 2 /* ATA interface out. */
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#define ATA_RX_DMA_NBR 3 /* ATA interface in. */
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#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */
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#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */
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#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */
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#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */
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#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
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#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
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#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */
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#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */
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#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */
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#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */
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#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */
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#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */
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#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */
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#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */
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#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */
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#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */
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#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */
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#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */
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#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */
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#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */
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#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */
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#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */
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enum dma_owner {
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dma_eth0,
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dma_eth1,
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dma_iop0,
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dma_iop1,
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dma_ser0,
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dma_ser1,
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dma_ser2,
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dma_ser3,
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dma_sser0,
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dma_sser1,
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dma_ata,
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dma_strp,
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dma_ext0,
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dma_ext1,
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dma_ext2,
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dma_ext3
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};
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int crisv32_request_dma(unsigned int dmanr, const char *device_id,
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unsigned options, unsigned bandwidth,
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enum dma_owner owner);
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void crisv32_free_dma(unsigned int dmanr);
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/* Masks used by crisv32_request_dma options: */
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#define DMA_VERBOSE_ON_ERROR 1
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#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
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#define DMA_INT_MEM 4
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#endif /* _ASM_ARCH_CRIS_DMA_H */
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