Qualcomm ARM64 DT updates for 5.11
For SM8250 the recently introduced support for handling boot-loader stream mappings in the ARM SMMU allow us to enable this, and thereby USB controller and PHY, SDHCI controller and FastRPC, as well as support for the SM8250 HDK board has been added. Additionally PRNG and RTC is enabled. Similarly for SM8150, the ARM SMMU could be added which allows the secondary USB controller and PHYs, as well as WiFi to be added and support for the SM8150 HDK board to be introduced. Additionally Coresight and support for the last-level cache controller was added. MSM8916 finally has VDDCX and VDDMX removed as regulators and are now handled by the rpmpd driver for the devices controlling them. The Longsheer L8150 gains touchscreen, sensors, vibrator and LED support. MSM8992 gains USB and SDHCI support as well as an I2C controller and the associated RMI4 based touchscreen for the Lumia 950. MSM8994 also gains USB and SDHCI support, as well as VADC and temp-alarm support. Then support for the Lumia 950 XL is added. SDM845 gains interconnect properties for a number of devices and the GENI wrappers gains iommu stream configuration, which means DMA operations on e.g. I2C now works. The Lenovo Yoga C630 finally has the SMMU enabled, a few fixes and the description of the eDP bridge and panel means that the laptop can now boot mainline with working display, GPU, WiFi and audio. SC7180 gains a slew of smaller improvements and fixes. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAl/FP0cbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FINAP/11hbDNRXJ+3oqLk53aD /8G0Xbyzy9gekpYURZwJJrjaGY7l1psM39Kbo+flUPusFfxRBNmbWrw57PPbzjyS d3RnPXuc/XDkOvCHtQstowtdKBl5EIXU6ec9xg4RY5bZUiD5Fpk8OLBAitvruEqy 6YCgMhy5yRspb8iBXA5N4ERU0EsQBOMIIoP6DRuGkeMkUhk/QllO+xwAr6ugI3Ot s3gua4tjWfi5kxT0bXklU4fk7Xeiuy6VL+giddd4dWVUm2GdO7jRlU6ae6CLoi2k PStZJcca8uOpTMpF4ZqMLNX51UAk+VZsCvjMm5pYIQAWCp15sWyMA20wi8vM+cjx HHhsXU7WAqQfLzMntgUd36CJaTuGw8J+QzQyNpQeHjbL6tAA15BfnIIQ+RUZWgsx XoPWdSvmUBhyo9g2cR7yXRXQGxvMRy/w7uHgv6Szb9KkDxeBnpYMjBMrbaZAsyMA YoYvhdIO9HkL2IbUxQgiszQsD58aDvauEY+KpOZclVW5ODPhJmsSTZK2aH/L6kj9 6hn0rOBrXy8rZE5Vs08C5D2WvqZ0Ib45vXNpb9uucvyXXNZMywGw+94B3YMNbkCz /C9C1DJcRX1NZjJnQco3Cn0Ni7AmRzD5aAHi3n2BhxbsxOxZ6v0SjEDbce+lXwYJ 5l4AcPSLDjGXFJsbUPQrHvJF =lkn4 -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DT updates for 5.11 For SM8250 the recently introduced support for handling boot-loader stream mappings in the ARM SMMU allow us to enable this, and thereby USB controller and PHY, SDHCI controller and FastRPC, as well as support for the SM8250 HDK board has been added. Additionally PRNG and RTC is enabled. Similarly for SM8150, the ARM SMMU could be added which allows the secondary USB controller and PHYs, as well as WiFi to be added and support for the SM8150 HDK board to be introduced. Additionally Coresight and support for the last-level cache controller was added. MSM8916 finally has VDDCX and VDDMX removed as regulators and are now handled by the rpmpd driver for the devices controlling them. The Longsheer L8150 gains touchscreen, sensors, vibrator and LED support. MSM8992 gains USB and SDHCI support as well as an I2C controller and the associated RMI4 based touchscreen for the Lumia 950. MSM8994 also gains USB and SDHCI support, as well as VADC and temp-alarm support. Then support for the Lumia 950 XL is added. SDM845 gains interconnect properties for a number of devices and the GENI wrappers gains iommu stream configuration, which means DMA operations on e.g. I2C now works. The Lenovo Yoga C630 finally has the SMMU enabled, a few fixes and the description of the eDP bridge and panel means that the laptop can now boot mainline with working display, GPU, WiFi and audio. SC7180 gains a slew of smaller improvements and fixes. * tag 'qcom-arm64-for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits) arm64: dts: qcom: c630: Define eDP bridge and panel arm64: dts: qcom: c630: Fix pinctrl pins properties arm64: dts: qcom: c630: Polish i2c-hid devices arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver arm64: dts: sdm845: Add interconnect properties for QUP interconnect: qcom: sdm845: Add the missing nodes for QUP dt-bindings: interconnect: sdm845: Add IDs for the QUP ports arm64: dts: qcom: c630: Expose LID events arm64: dts: qcom: c630: Re-enable apps_smmu dts: qcom: sdm845: Add dt entries to support crypto engine. arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD arm64: dts: qcom: sdm845: use GIC_SPI for IPA interrupts arm64: dts: qcom: sc7180: use GIC_SPI for IPA interrupts arm64: dts: qcom: sc7180: limit IPA iommu streams arm64: dts: qcom: sm8150: Add Coresight support arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite arm64: dts: qcom: sc7180-trogdor: add "pen-insert" label for trogdor arm64: qcom: sc7180: trogdor: Add ADC nodes and thermal zone for charger thermistor ... Link: https://lore.kernel.org/r/20201130190131.345187-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
a39d2ef78d
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@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
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@ -26,6 +27,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
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@ -41,5 +45,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
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@ -417,11 +417,6 @@
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vdd_l4_l5_l6-supply = <&pm8916_s4>;
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vdd_l7-supply = <&pm8916_s4>;
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s1 {
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regulator-min-microvolt = <375000>;
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regulator-max-microvolt = <1562000>;
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};
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s3 {
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regulator-min-microvolt = <375000>;
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regulator-max-microvolt = <1562000>;
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@ -445,11 +440,6 @@
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regulator-max-microvolt = <1200000>;
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};
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l3 {
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regulator-min-microvolt = <375000>;
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regulator-max-microvolt = <1525000>;
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};
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l4 {
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <3337000>;
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@ -156,8 +156,8 @@
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no-map;
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};
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tz: tz@48500000 {
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reg = <0x0 0x48500000 0x0 0x00200000>;
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tz: memory@4a600000 {
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reg = <0x0 0x4a600000 0x0 0x00400000>;
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no-map;
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};
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@ -167,7 +167,7 @@
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};
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q6_region: memory@4ab00000 {
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reg = <0x0 0x4ab00000 0x0 0x02800000>;
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reg = <0x0 0x4ab00000 0x0 0x05500000>;
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no-map;
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};
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};
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@ -179,22 +179,22 @@
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x0 0xffffffff>;
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dma-ranges;
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compatible = "simple-bus";
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prng: qrng@e1000 {
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compatible = "qcom,prng-ee";
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reg = <0xe3000 0x1000>;
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reg = <0x0 0xe3000 0x0 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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cryptobam: dma@704000 {
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cryptobam: dma-controller@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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reg = <0x0 0x00704000 0x0 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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@ -206,7 +206,7 @@
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crypto: crypto@73a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x0073a000 0x6000>;
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reg = <0x0 0x0073a000 0x0 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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@ -217,7 +217,7 @@
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq6018-pinctrl";
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reg = <0x01000000 0x300000>;
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reg = <0x0 0x01000000 0x0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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@ -235,7 +235,7 @@
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x01800000 0x80000>;
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reg = <0x0 0x01800000 0x0 0x80000>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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@ -244,17 +244,17 @@
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tcsr_mutex_regs: syscon@1905000 {
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compatible = "syscon";
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reg = <0x01905000 0x8000>;
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reg = <0x0 0x01905000 0x0 0x8000>;
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};
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tcsr_q6: syscon@1945000 {
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compatible = "syscon";
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reg = <0x01945000 0xe000>;
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reg = <0x0 0x01945000 0x0 0xe000>;
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};
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blsp_dma: dma@7884000 {
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x2b000>;
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reg = <0x0 0x07884000 0x0 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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@ -264,7 +264,7 @@
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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reg = <0x0 0x078b1000 0x0 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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@ -276,7 +276,7 @@
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b5000 0x600>;
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reg = <0x0 0x078b5000 0x0 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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@ -291,7 +291,7 @@
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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@ -306,7 +306,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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reg = <0x0 0x078b6000 0x0 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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@ -321,7 +321,7 @@
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b7000 0x600>;
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reg = <0x0 0x078b7000 0x0 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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@ -336,24 +336,24 @@
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0b000000 0x1000>, /*GICD*/
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<0x0b002000 0x1000>, /*GICC*/
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<0x0b001000 0x1000>, /*GICH*/
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<0x0b004000 0x1000>; /*GICV*/
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reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
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<0x0 0x0b002000 0x0 0x1000>, /*GICC*/
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<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
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<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@b017000 {
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compatible = "qcom,kpss-wdt";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0b017000 0x40>;
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reg = <0x0 0x0b017000 0x0 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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};
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq6018-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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reg = <0x0 0x0b111000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&a53pll>, <&xo>;
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clock-names = "pll", "xo";
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@ -362,7 +362,7 @@
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a53pll: clock@b116000 {
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compatible = "qcom,ipq6018-a53pll";
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reg = <0x0b116000 0x40>;
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reg = <0x0 0x0b116000 0x0 0x40>;
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#clock-cells = <0>;
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clocks = <&xo>;
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clock-names = "xo";
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@ -377,68 +377,68 @@
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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reg = <0x0 0x0b120000 0x0 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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reg = <0x0 0x0b121000 0x0 0x1000>,
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<0x0 0x0b122000 0x0 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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reg = <0x0 0xb123000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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reg = <0x0 0x0b124000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b125000 0x1000>;
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reg = <0x0 0x0b125000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b126000 0x1000>;
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reg = <0x0 0x0b126000 0x0 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b127000 0x1000>;
|
||||
reg = <0x0 0x0b127000 0x0 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@b128000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0b128000 0x1000>;
|
||||
reg = <0x0 0x0b128000 0x0 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
q6v5_wcss: remoteproc@cd00000 {
|
||||
compatible = "qcom,ipq8074-wcss-pil";
|
||||
reg = <0x0cd00000 0x4040>,
|
||||
<0x004ab000 0x20>;
|
||||
reg = <0x0 0x0cd00000 0x0 0x4040>,
|
||||
<0x0 0x004ab000 0x0 0x20>;
|
||||
reg-names = "qdsp6",
|
||||
"rmb";
|
||||
interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
|
||||
|
|
|
|||
|
|
@ -276,7 +276,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
blsp_dma: dma-controller@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x2b000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -372,7 +372,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
qpic_bam: dma@7984000 {
|
||||
qpic_bam: dma-controller@7984000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07984000 0x1a000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@
|
|||
#include "msm8916-pm8916.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "Longcheer L8150";
|
||||
|
|
@ -50,6 +52,139 @@
|
|||
linux,code = <KEY_VOLUMEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_ctp: regulator-ctp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ctp";
|
||||
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ctp_pwr_en_default>;
|
||||
};
|
||||
|
||||
flash-led-controller {
|
||||
compatible = "sgmicro,sgm3140";
|
||||
flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&camera_flash_default>;
|
||||
|
||||
flash_led: led {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
flash-max-timeout-us = <250000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c1 {
|
||||
status = "okay";
|
||||
|
||||
led-controller@45 {
|
||||
compatible = "awinic,aw2013";
|
||||
reg = <0x45>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vcc-supply = <&pm8916_l17>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
led-max-microamp = <5000>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
led-max-microamp = <5000>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
led-max-microamp = <5000>;
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c2 {
|
||||
status = "okay";
|
||||
|
||||
accelerometer@10 {
|
||||
compatible = "bosch,bmc150_accel";
|
||||
reg = <0x10>;
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
|
||||
mount-matrix = "0", "1", "0",
|
||||
"-1", "0", "0",
|
||||
"0", "0", "1";
|
||||
};
|
||||
|
||||
magnetometer@12 {
|
||||
compatible = "bosch,bmc150_magn";
|
||||
reg = <0x12>;
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
|
||||
gyroscope@68 {
|
||||
compatible = "bosch,bmg160";
|
||||
reg = <0x68>;
|
||||
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gyro_int_default>;
|
||||
|
||||
vdd-supply = <&pm8916_l17>;
|
||||
vddio-supply = <&pm8916_l6>;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
status = "okay";
|
||||
|
||||
rmi4@20 {
|
||||
compatible = "syna,rmi4-i2c";
|
||||
reg = <0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
vdd-supply = <®_ctp>;
|
||||
vio-supply = <&pm8916_l6>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tp_int_default>;
|
||||
|
||||
syna,startup-delay-ms = <10>;
|
||||
|
||||
rmi4-f01@1 {
|
||||
reg = <0x1>;
|
||||
syna,nosleep-mode = <1>; // Allow sleeping
|
||||
};
|
||||
|
||||
rmi4-f12@12 {
|
||||
reg = <0x12>;
|
||||
syna,sensor-type = <1>; // Touchscreen
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
|
|
@ -61,6 +196,10 @@
|
|||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
|
||||
&pm8916_vib {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pronto {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -98,11 +237,6 @@
|
|||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
s1 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
|
|
@ -123,11 +257,6 @@
|
|||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
l3 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1287500>;
|
||||
};
|
||||
|
||||
l4 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
|
|
@ -207,6 +336,22 @@
|
|||
};
|
||||
|
||||
&msmgpio {
|
||||
camera_flash_default: camera-flash-default {
|
||||
pins = "gpio31", "gpio32";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ctp_pwr_en_default: ctp-pwr-en-default {
|
||||
pins = "gpio17";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
gpio_keys_default: gpio-keys-default {
|
||||
pins = "gpio107";
|
||||
function = "gpio";
|
||||
|
|
@ -215,6 +360,22 @@
|
|||
bias-pull-up;
|
||||
};
|
||||
|
||||
gyro_int_default: gyro-int-default {
|
||||
pins = "gpio23";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tp_int_default: tp-int-default {
|
||||
pins = "gpio13";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
usb_vbus_default: usb-vbus-default {
|
||||
pins = "gpio62";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -17,13 +17,10 @@
|
|||
};
|
||||
|
||||
&mpss {
|
||||
cx-supply = <&pm8916_s1>;
|
||||
mx-supply = <&pm8916_l3>;
|
||||
pll-supply = <&pm8916_l7>;
|
||||
};
|
||||
|
||||
&pronto {
|
||||
vddmx-supply = <&pm8916_l3>;
|
||||
vddpx-supply = <&pm8916_l7>;
|
||||
|
||||
iris {
|
||||
|
|
@ -53,13 +50,13 @@
|
|||
smd_rpm_regulators: pm8916-regulators {
|
||||
compatible = "qcom,rpm-pm8916-regulators";
|
||||
|
||||
pm8916_s1: s1 {};
|
||||
/* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
|
||||
pm8916_s3: s3 {};
|
||||
pm8916_s4: s4 {};
|
||||
|
||||
pm8916_l1: l1 {};
|
||||
pm8916_l2: l2 {};
|
||||
pm8916_l3: l3 {};
|
||||
/* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
|
||||
pm8916_l4: l4 {};
|
||||
pm8916_l5: l5 {};
|
||||
pm8916_l6: l6 {};
|
||||
|
|
|
|||
|
|
@ -78,6 +78,9 @@
|
|||
sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&muic_i2c_default>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
|
@ -164,11 +167,6 @@
|
|||
vdd_l4_l5_l6-supply = <&pm8916_s4>;
|
||||
vdd_l7-supply = <&pm8916_s4>;
|
||||
|
||||
s1 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
|
||||
s3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
|
|
@ -189,11 +187,6 @@
|
|||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
l3 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1287500>;
|
||||
};
|
||||
|
||||
l4 {
|
||||
regulator-min-microvolt = <2050000>;
|
||||
regulator-max-microvolt = <2050000>;
|
||||
|
|
@ -314,6 +307,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
muic_i2c_default: muic-i2c-default {
|
||||
pins = "gpio105", "gpio106";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
muic_int_default: muic-int-default {
|
||||
pins = "gpio12";
|
||||
function = "gpio";
|
||||
|
|
|
|||
|
|
@ -28,6 +28,27 @@
|
|||
"0", "0", "1";
|
||||
};
|
||||
|
||||
&blsp_i2c5 {
|
||||
status = "okay";
|
||||
|
||||
touchscreen@20 {
|
||||
compatible = "zinitix,bt541";
|
||||
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
touchscreen-size-x = <540>;
|
||||
touchscreen-size-y = <960>;
|
||||
|
||||
vdd-supply = <®_vdd_tsp>;
|
||||
vddo-supply = <&pm8916_l6>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ts_int_default>;
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
panel@0 {
|
||||
reg = <0>;
|
||||
|
|
@ -59,4 +80,12 @@
|
|||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
ts_int_default: ts-int-default {
|
||||
pins = "gpio13";
|
||||
function = "gpio";
|
||||
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,msm8916.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
|
|
@ -289,6 +290,35 @@
|
|||
compatible = "qcom,rpmcc-msm8916";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rpmpd: power-controller {
|
||||
compatible = "qcom,msm8916-rpmpd";
|
||||
#power-domain-cells = <1>;
|
||||
operating-points-v2 = <&rpmpd_opp_table>;
|
||||
|
||||
rpmpd_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
rpmpd_opp_ret: opp1 {
|
||||
opp-level = <1>;
|
||||
};
|
||||
rpmpd_opp_svs_krait: opp2 {
|
||||
opp-level = <2>;
|
||||
};
|
||||
rpmpd_opp_svs_soc: opp3 {
|
||||
opp-level = <3>;
|
||||
};
|
||||
rpmpd_opp_nom: opp4 {
|
||||
opp-level = <4>;
|
||||
};
|
||||
rpmpd_opp_turbo: opp5 {
|
||||
opp-level = <5>;
|
||||
};
|
||||
rpmpd_opp_super_turbo: opp6 {
|
||||
opp-level = <6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1263,6 +1293,10 @@
|
|||
interrupt-names = "wdog", "fatal", "ready",
|
||||
"handover", "stop-ack";
|
||||
|
||||
power-domains = <&rpmpd MSM8916_VDDCX>,
|
||||
<&rpmpd MSM8916_VDDMX>;
|
||||
power-domain-names = "cx", "mx";
|
||||
|
||||
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
|
||||
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
|
||||
<&gcc GCC_BOOT_ROM_AHB_CLK>,
|
||||
|
|
@ -1391,7 +1425,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_dma: dma@7884000 {
|
||||
blsp_dma: dma-controller@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x23000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1660,6 +1694,10 @@
|
|||
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
|
||||
|
||||
power-domains = <&rpmpd MSM8916_VDDCX>,
|
||||
<&rpmpd MSM8916_VDDMX>;
|
||||
power-domain-names = "cx", "mx";
|
||||
|
||||
qcom,state = <&wcnss_smp2p_out 0>;
|
||||
qcom,state-names = "stop";
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
&blsp_i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rmi4-i2c-dev@4b {
|
||||
compatible = "syna,rmi4-i2c";
|
||||
reg = <0x4b>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
rmi4-f01@1 {
|
||||
reg = <0x01>;
|
||||
syna,nosleep-mode = <1>;
|
||||
};
|
||||
|
||||
rmi4-f12@12 {
|
||||
reg = <0x12>;
|
||||
syna,sensor-type = <1>;
|
||||
syna,clip-x-low = <0>;
|
||||
syna,clip-x-high = <1440>;
|
||||
syna,clip-y-low = <0>;
|
||||
syna,clip-y-high = <2560>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhc_1 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -242,6 +242,37 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb3: usb@f92f8800 {
|
||||
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
||||
reg = <0xf92f8800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB30_MASTER_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
|
||||
clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <120000000>;
|
||||
|
||||
power-domains = <&gcc USB30_GDSC>;
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
|
||||
dwc3@f9200000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xf9200000 0xcc00>;
|
||||
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
};
|
||||
|
||||
sdhc_1: sdhci@f9824900 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
|
||||
|
|
@ -269,6 +300,29 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhc_2: sdhci@f98a4900 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
||||
reg-names = "hc_mem", "core_mem";
|
||||
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "core", "iface", "xo";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
|
||||
cd-gpios = <&tlmm 100 0>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@f991e000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf991e000 0x1000>;
|
||||
|
|
@ -282,6 +336,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_i2c1: i2c@f9923000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0xf9923000 0x500>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
|
||||
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
|
||||
clock-names = "iface", "core";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_default>;
|
||||
pinctrl-1 = <&i2c1_sleep>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp_i2c2: i2c@f9924000 {
|
||||
compatible = "qcom,i2c-qup-v2.2.1";
|
||||
reg = <0xf9924000 0x500>;
|
||||
|
|
@ -502,6 +572,20 @@
|
|||
bias-pull-down;
|
||||
};
|
||||
|
||||
i2c1_default: i2c1-default {
|
||||
function = "blsp_i2c1";
|
||||
pins = "gpio2", "gpio3";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
i2c1_sleep: i2c1-sleep {
|
||||
function = "gpio";
|
||||
pins = "gpio2", "gpio3";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
i2c2_default: i2c2-default {
|
||||
function = "blsp_i2c2";
|
||||
pins = "gpio6", "gpio7";
|
||||
|
|
@ -573,6 +657,42 @@
|
|||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
sdc2_clk_on: sdc2-clk-on {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
sdc2_clk_off: sdc2-clk-off {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
sdc2_cmd_on: sdc2-cmd-on {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
sdc2_cmd_off: sdc2-cmd-off {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
sdc2_data_on: sdc2-data-on {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
sdc2_data_off: sdc2-data-off {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2020, Konrad Dybcio
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8994.dtsi"
|
||||
#include "pm8994.dtsi"
|
||||
#include "pmi8994.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Microsoft Lumia 950 XL";
|
||||
compatible = "microsoft,cityman", "qcom,msm8994";
|
||||
|
||||
/*
|
||||
* Most Lumia 950XL users use GRUB to load their kernels,
|
||||
* hence there is no need for msm-id and friends.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This enables graphical output via bootloader-enabled display.
|
||||
* acpi=no is required due to WP platforms having ACPI support, but
|
||||
* only for Windows-based OSes.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "earlycon=efifb console=efifb acpi=no";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rmi4-i2c-dev@4b {
|
||||
compatible = "syna,rmi4-i2c";
|
||||
reg = <0x4b>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
rmi4-f01@1 {
|
||||
reg = <0x01>;
|
||||
syna,nosleep-mode = <1>;
|
||||
};
|
||||
|
||||
rmi4-f12@12 {
|
||||
reg = <0x12>;
|
||||
syna,sensor-type = <1>;
|
||||
syna,clip-x-low = <0>;
|
||||
syna,clip-x-high = <1440>;
|
||||
syna,clip-y-low = <0>;
|
||||
syna,clip-y-high = <2660>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp2_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -282,6 +282,37 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb3: usb@f92f8800 {
|
||||
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
||||
reg = <0xf92f8800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB30_MASTER_CLK>,
|
||||
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SLEEP_CLK>,
|
||||
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
|
||||
clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <120000000>;
|
||||
|
||||
power-domains = <&gcc USB30_GDSC>;
|
||||
qcom,select-utmi-as-pipe-clk;
|
||||
|
||||
dwc3@f9200000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xf9200000 0xcc00>;
|
||||
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
};
|
||||
|
||||
sdhc1: sdhci@f9824900 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
|
||||
|
|
@ -305,7 +336,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma@f9904000 {
|
||||
sdhc2: sdhci@f98a4900 {
|
||||
compatible = "qcom,sdhci-msm-v4";
|
||||
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
|
||||
reg-names = "hc_mem", "core_mem";
|
||||
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "core", "iface", "xo";
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
|
||||
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
|
||||
|
||||
cd-gpios = <&tlmm 100 0>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma-controller@f9904000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0xf9904000 0x19000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -401,7 +455,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_dma: dma@f9944000 {
|
||||
blsp2_dma: dma-controller@f9944000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0xf9944000 0x19000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -683,6 +737,42 @@
|
|||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
sdc2_clk_on: sdc2-clk-on {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
sdc2_clk_off: sdc2-clk-off {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
sdc2_cmd_on: sdc2-cmd-on {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
sdc2_cmd_off: sdc2-cmd-off {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
sdc2_data_on: sdc2-data-on {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <10>;
|
||||
};
|
||||
|
||||
sdc2_data_off: sdc2-data-off {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1990,7 +1990,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
slimbam: dma@9184000 {
|
||||
slimbam: dma-controller@9184000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
qcom,controlled-remotely;
|
||||
reg = <0x09184000 0x32000>;
|
||||
|
|
|
|||
|
|
@ -1754,7 +1754,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma@c144000 {
|
||||
blsp1_dma: dma-controller@c144000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x0c144000 0x25000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -52,6 +52,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
pm6150_adc_tm: adc-tm@3500 {
|
||||
compatible = "qcom,spmi-adc-tm5";
|
||||
reg = <0x3500>;
|
||||
interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pm6150_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,30 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pm6150l_adc: adc@3100 {
|
||||
compatible = "qcom,spmi-adc5";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
adc-chan@6 {
|
||||
reg = <ADC5_DIE_TEMP>;
|
||||
label = "die_temp";
|
||||
};
|
||||
};
|
||||
|
||||
pm6150l_adc_tm: adc-tm@3500 {
|
||||
compatible = "qcom,spmi-adc-tm5";
|
||||
reg = <0x3500>;
|
||||
interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pm6150l_gpio: gpios@c000 {
|
||||
compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
rtc@6000 {
|
||||
pm8150_rtc: rtc@6000 {
|
||||
compatible = "qcom,pm8941-rtc";
|
||||
reg = <0x6000>;
|
||||
reg-names = "rtc", "alarm";
|
||||
|
|
|
|||
|
|
@ -1,7 +1,32 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <dt-bindings/iio/qcom,spmi-vadc.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
pm8994 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
|
||||
thermal-sensors = <&pm8994_temp>;
|
||||
|
||||
trips {
|
||||
pm8994_alert0: pm8994-alert0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
pm8994_crit: pm8994-crit {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
|
||||
|
|
@ -35,33 +60,56 @@
|
|||
|
||||
};
|
||||
|
||||
pm8994_temp: temp-alarm@2400 {
|
||||
compatible = "qcom,spmi-temp-alarm";
|
||||
reg = <0x2400>;
|
||||
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
io-channels = <&pm8994_vadc VADC_DIE_TEMP>;
|
||||
io-channel-names = "thermal";
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
pm8994_vadc: adc@3100 {
|
||||
compatible = "qcom,spmi-vadc";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
adc-chan@7 {
|
||||
reg = <VADC_VSYS>;
|
||||
qcom,pre-scaling = <1 3>;
|
||||
label = "vph_pwr";
|
||||
};
|
||||
adc-chan@8 {
|
||||
reg = <VADC_DIE_TEMP>;
|
||||
label = "die_temp";
|
||||
};
|
||||
adc-chan@9 {
|
||||
reg = <VADC_REF_625MV>;
|
||||
label = "ref_625mv";
|
||||
};
|
||||
adc-chan@a {
|
||||
reg = <VADC_REF_1250MV>;
|
||||
label = "ref_1250mv";
|
||||
};
|
||||
adc-chan@e {
|
||||
reg = <VADC_GND_REF>;
|
||||
};
|
||||
adc-chan@f {
|
||||
reg = <VADC_VDD_VADC>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8994_gpios: gpios@c000 {
|
||||
compatible = "qcom,pm8994-gpio";
|
||||
compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
|
||||
reg = <0xc000>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pm8994_gpios 0 0 22>;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc5 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc6 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc7 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc8 0 IRQ_TYPE_NONE>,
|
||||
<0 0xc9 0 IRQ_TYPE_NONE>,
|
||||
<0 0xca 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcb 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcc 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcd 0 IRQ_TYPE_NONE>,
|
||||
<0 0xce 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcf 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd2 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd3 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd4 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd5 0 IRQ_TYPE_NONE>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pm8994_mpps: mpps@a000 {
|
||||
|
|
|
|||
|
|
@ -801,7 +801,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma@7884000 {
|
||||
blsp1_dma: dma-controller@7884000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07884000 0x25000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1045,7 +1045,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_dma: dma@7ac4000 {
|
||||
blsp2_dma: dma-controller@7ac4000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x07ac4000 0x17000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -18,12 +18,20 @@
|
|||
|
||||
aliases {
|
||||
serial0 = &uart12;
|
||||
sdhc2 = &sdhc_2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
/* Fixed crystal oscillator dedicated to MCP2518FD */
|
||||
clk40M: can_clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
|
||||
dc12v: dc12v-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DC12V";
|
||||
|
|
@ -459,6 +467,10 @@
|
|||
"PM3003A_MODE";
|
||||
};
|
||||
|
||||
&pm8150_rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -471,9 +483,33 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
|
||||
vmmc-supply = <&vreg_l9c_2p96>;
|
||||
vqmmc-supply = <&vreg_l6c_2p96>;
|
||||
cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
/* there seem to be issues with HS400-1.8V mode, so disable it */
|
||||
no-1-8-v;
|
||||
no-sdio;
|
||||
no-emmc;
|
||||
};
|
||||
|
||||
/* CAN */
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
can@0 {
|
||||
compatible = "microchip,mcp2518fd";
|
||||
reg = <0>;
|
||||
clocks = <&clk40M>;
|
||||
interrupts-extended = <&tlmm 15 IRQ_TYPE_LEVEL_LOW>;
|
||||
spi-max-frequency = <10000000>;
|
||||
vdd-supply = <&vdc_5v>;
|
||||
xceiver-supply = <&vdc_5v>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
|
|
@ -659,6 +695,32 @@
|
|||
"HST_BLE_SNS_UART_RX",
|
||||
"HST_WLAN_UART_TX",
|
||||
"HST_WLAN_UART_RX";
|
||||
|
||||
sdc2_default_state: sdc2-default {
|
||||
clk {
|
||||
pins = "sdc2_clk";
|
||||
bias-disable;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
cmd {
|
||||
pins = "sdc2_cmd";
|
||||
bias-pull-up;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
|
||||
data {
|
||||
pins = "sdc2_data";
|
||||
bias-pull-up;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
sdc2_card_det_n: sd-card-det-n {
|
||||
pins = "gpio77";
|
||||
function = "gpio";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&uart12 {
|
||||
|
|
@ -684,3 +746,49 @@
|
|||
vdda-pll-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-max-microamp = <18800>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l5a_0p88>;
|
||||
vdda33-supply = <&vreg_l2a_3p1>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l18a_0p92>;
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-pll-supply = <&vreg_l5a_0p88>;
|
||||
vdda33-supply = <&vreg_l2a_3p1>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
};
|
||||
|
||||
&usb_2_qmpphy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l18a_0p92>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* SC7180 lite device tree source
|
||||
*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
&cpu6_opp10 {
|
||||
opp-peak-kBps = <7216000 22425600>;
|
||||
};
|
||||
|
||||
&cpu6_opp11 {
|
||||
opp-peak-kBps = <7216000 22425600>;
|
||||
};
|
||||
|
||||
&cpu6_opp12 {
|
||||
opp-peak-kBps = <8532000 23347200>;
|
||||
};
|
||||
|
|
@ -14,6 +14,17 @@
|
|||
compatible = "google,lazor-rev0", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&pp3300_hub {
|
||||
/* pp3300_l7c is used to power the USB hub */
|
||||
/delete-property/regulator-always-on;
|
||||
/delete-property/regulator-boot-on;
|
||||
};
|
||||
|
||||
&pp3300_l7c {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
&sn65dsi86_out {
|
||||
/*
|
||||
* Lane 0 was incorrectly mapped on the cable, but we've now decided
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@
|
|||
#include "sc7180-trogdor-lazor-r1.dts"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev1+) with KB Backlight";
|
||||
compatible = "google,lazor-sku2", "qcom,sc7180";
|
||||
model = "Google Lazor (rev1 - 2) with KB Backlight";
|
||||
compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
|
|
|
|||
|
|
@ -9,8 +9,16 @@
|
|||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev1+) with LTE";
|
||||
compatible = "google,lazor-sku0", "qcom,sc7180";
|
||||
model = "Google Lazor (rev1 - 2) with LTE";
|
||||
compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&ap_sar_sensor {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_sar_sensor_i2c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
|
|
|
|||
|
|
@ -10,6 +10,17 @@
|
|||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev1+)";
|
||||
compatible = "google,lazor", "qcom,sc7180";
|
||||
model = "Google Lazor (rev1 - 2)";
|
||||
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&pp3300_hub {
|
||||
/* pp3300_l7c is used to power the USB hub */
|
||||
/delete-property/regulator-always-on;
|
||||
/delete-property/regulator-boot-on;
|
||||
};
|
||||
|
||||
&pp3300_l7c {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
#include "sc7180-trogdor-lazor-r3.dts"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+) with KB Backlight";
|
||||
compatible = "google,lazor-sku2", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
#include "sc7180-trogdor-lazor-r3.dts"
|
||||
#include "sc7180-trogdor-lte-sku.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+) with LTE";
|
||||
compatible = "google,lazor-sku0", "qcom,sc7180";
|
||||
};
|
||||
|
||||
&ap_sar_sensor {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_sar_sensor_i2c {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&keyboard_backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Google Lazor board device tree source
|
||||
*
|
||||
* Copyright 2020 Google LLC.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc7180-trogdor-lazor.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Lazor (rev3+)";
|
||||
compatible = "google,lazor", "qcom,sc7180";
|
||||
};
|
||||
|
|
@ -30,7 +30,12 @@ ap_h1_spi: &spi0 {};
|
|||
};
|
||||
|
||||
&ap_sar_sensor {
|
||||
status = "okay";
|
||||
semtech,cs0-ground;
|
||||
semtech,combined-sensors = <3>;
|
||||
semtech,resolution = "fine";
|
||||
semtech,startup-sensor = <0>;
|
||||
semtech,proxraw-strength = <8>;
|
||||
semtech,avg-pos-strength = <64>;
|
||||
};
|
||||
|
||||
ap_ts_pen_1v8: &i2c4 {
|
||||
|
|
|
|||
|
|
@ -9,6 +9,10 @@
|
|||
label = "proximity-wifi-lte";
|
||||
};
|
||||
|
||||
&mpss_mem {
|
||||
reg = <0x0 0x86000000 0x0 0x8c00000>;
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn",
|
||||
"qcom/sc7180-trogdor/modem/qdsp6sw.mbn";
|
||||
|
|
|
|||
|
|
@ -34,11 +34,6 @@ ap_h1_spi: &spi0 {};
|
|||
};
|
||||
};
|
||||
|
||||
&ap_sar_sensor_i2c {
|
||||
/* Not hooked up */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ap_ts_pen_1v8: &i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -58,6 +53,17 @@ ap_ts_pen_1v8: &i2c4 {
|
|||
};
|
||||
};
|
||||
|
||||
&pp3300_hub {
|
||||
/* pp3300_l7c is used to power the USB hub */
|
||||
/delete-property/regulator-always-on;
|
||||
/delete-property/regulator-boot-on;
|
||||
};
|
||||
|
||||
&pp3300_l7c {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,6 +13,23 @@
|
|||
#include "pm6150.dtsi"
|
||||
#include "pm6150l.dtsi"
|
||||
|
||||
/ {
|
||||
thermal-zones {
|
||||
charger-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&pm6150_adc_tm 1>;
|
||||
|
||||
trips {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Reserved memory changes
|
||||
*
|
||||
|
|
@ -39,7 +56,7 @@
|
|||
};
|
||||
|
||||
mpss_mem: memory@86000000 {
|
||||
reg = <0x0 0x86000000 0x0 0x8c00000>;
|
||||
reg = <0x0 0x86000000 0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
|
|
@ -174,11 +191,38 @@
|
|||
vin-supply = <&pp3300_a>;
|
||||
};
|
||||
|
||||
pp3300_hub: pp3300-hub {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pp3300_hub";
|
||||
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&en_pp3300_hub>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
vin-supply = <&pp3300_a>;
|
||||
};
|
||||
|
||||
/* BOARD-SPECIFIC TOP LEVEL NODES */
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
|
||||
/* The panels don't seem to like anything below ~ 5% */
|
||||
brightness-levels = <
|
||||
196 256 324 400 484 576 676 784 900 1024 1156 1296
|
||||
1444 1600 1764 1936 2116 2304 2500 2704 2916 3136
|
||||
3364 3600 3844 4096
|
||||
>;
|
||||
num-interpolated-steps = <64>;
|
||||
default-brightness-level = <951>;
|
||||
|
||||
pwms = <&cros_ec_pwm 1>;
|
||||
enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&ppvar_sys>;
|
||||
|
|
@ -192,7 +236,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pen_pdct_l>;
|
||||
|
||||
pen-insert {
|
||||
pen_insert: pen-insert {
|
||||
label = "Pen Insert";
|
||||
|
||||
/* Insert = low, eject = high */
|
||||
|
|
@ -469,13 +513,10 @@
|
|||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
pp3300_hub:
|
||||
pp3300_l7c: ldo7 {
|
||||
regulator-min-microvolt = <3304000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
pp1800_brij_vccio:
|
||||
|
|
@ -645,7 +686,6 @@ edp_brij_i2c: &i2c2 {
|
|||
};
|
||||
|
||||
ap_sar_sensor_i2c: &i2c5 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
ap_sar_sensor: proximity@28 {
|
||||
|
|
@ -733,6 +773,25 @@ hp_i2c: &i2c9 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pm6150_adc {
|
||||
charger-thermistor@4f {
|
||||
reg = <ADC5_AMUX_THM3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm6150_adc_tm {
|
||||
status = "okay";
|
||||
|
||||
charger-thermistor@1 {
|
||||
reg = <1>;
|
||||
io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&pm6150_pwrkey {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -776,7 +835,20 @@ hp_i2c: &i2c9 {
|
|||
cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-0 = <&qup_spi0_cs_gpio>;
|
||||
cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi6 {
|
||||
pinctrl-0 = <&qup_spi6_cs_gpio>;
|
||||
cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
ap_spi_fp: &spi10 {
|
||||
pinctrl-0 = <&qup_spi10_cs_gpio>;
|
||||
cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
|
||||
|
||||
cros_ec_fp: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
|
|
@ -937,7 +1009,7 @@ ap_spi_fp: &spi10 {
|
|||
};
|
||||
};
|
||||
|
||||
&qup_spi0_default {
|
||||
&qup_spi0_cs_gpio {
|
||||
pinconf {
|
||||
pins = "gpio34", "gpio35", "gpio36", "gpio37";
|
||||
drive-strength = <2>;
|
||||
|
|
@ -945,7 +1017,7 @@ ap_spi_fp: &spi10 {
|
|||
};
|
||||
};
|
||||
|
||||
&qup_spi6_default {
|
||||
&qup_spi6_cs_gpio {
|
||||
pinconf {
|
||||
pins = "gpio59", "gpio60", "gpio61", "gpio62";
|
||||
drive-strength = <2>;
|
||||
|
|
@ -953,7 +1025,7 @@ ap_spi_fp: &spi10 {
|
|||
};
|
||||
};
|
||||
|
||||
&qup_spi10_default {
|
||||
&qup_spi10_cs_gpio {
|
||||
pinconf {
|
||||
pins = "gpio86", "gpio87", "gpio88", "gpio89";
|
||||
drive-strength = <2>;
|
||||
|
|
@ -1164,6 +1236,19 @@ ap_spi_fp: &spi10 {
|
|||
};
|
||||
};
|
||||
|
||||
en_pp3300_hub: en-pp3300-hub {
|
||||
pinmux {
|
||||
pins = "gpio84";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio84";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
fpmcu_boot0: fpmcu-boot0 {
|
||||
pinmux {
|
||||
pins = "gpio10";
|
||||
|
|
@ -1310,7 +1395,8 @@ ap_spi_fp: &spi10 {
|
|||
|
||||
pinconf {
|
||||
pins = "gpio24";
|
||||
bias-pull-up;
|
||||
/* Has external pullup */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* SC7180 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
|
|
@ -31,6 +31,8 @@
|
|||
chosen { };
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdhc_1;
|
||||
mmc2 = &sdhc_2;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
|
|
@ -525,6 +527,11 @@
|
|||
opp-hz = /bits/ 64 <2400000000>;
|
||||
opp-peak-kBps = <8532000 23347200>;
|
||||
};
|
||||
|
||||
cpu6_opp16: opp-2553600000 {
|
||||
opp-hz = /bits/ 64 <2553600000>;
|
||||
opp-peak-kBps = <8532000 23347200>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
|
|
@ -660,7 +667,7 @@
|
|||
};
|
||||
|
||||
qfprom: efuse@784000 {
|
||||
compatible = "qcom,qfprom";
|
||||
compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
|
||||
reg = <0 0x00784000 0 0x8ff>,
|
||||
<0 0x00780000 0 0x7a0>,
|
||||
<0 0x00782000 0 0x100>,
|
||||
|
|
@ -1394,7 +1401,8 @@
|
|||
ipa: ipa@1e40000 {
|
||||
compatible = "qcom,sc7180-ipa";
|
||||
|
||||
iommus = <&apps_smmu 0x440 0x3>;
|
||||
iommus = <&apps_smmu 0x440 0x0>,
|
||||
<&apps_smmu 0x442 0x0>;
|
||||
reg = <0 0x1e40000 0 0x7000>,
|
||||
<0 0x1e47000 0 0x2000>,
|
||||
<0 0x1e04000 0 0x2c000>;
|
||||
|
|
@ -1402,8 +1410,8 @@
|
|||
"ipa-shared",
|
||||
"gsi";
|
||||
|
||||
interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ipa",
|
||||
|
|
@ -1595,6 +1603,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi0_cs_gpio: qup-spi0-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio34", "gpio35",
|
||||
"gpio36";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio37";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi1_default: qup-spi1-default {
|
||||
pinmux {
|
||||
pins = "gpio0", "gpio1",
|
||||
|
|
@ -1603,6 +1624,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi1_cs_gpio: qup-spi1-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio0", "gpio1",
|
||||
"gpio2";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio3";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi3_default: qup-spi3-default {
|
||||
pinmux {
|
||||
pins = "gpio38", "gpio39",
|
||||
|
|
@ -1611,6 +1645,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi3_cs_gpio: qup-spi3-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio38", "gpio39",
|
||||
"gpio40";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio41";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi5_default: qup-spi5-default {
|
||||
pinmux {
|
||||
pins = "gpio25", "gpio26",
|
||||
|
|
@ -1619,6 +1666,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi5_cs_gpio: qup-spi5-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio25", "gpio26",
|
||||
"gpio27";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi6_default: qup-spi6-default {
|
||||
pinmux {
|
||||
pins = "gpio59", "gpio60",
|
||||
|
|
@ -1627,6 +1687,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi6_cs_gpio: qup-spi6-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio59", "gpio60",
|
||||
"gpio61";
|
||||
function = "qup10";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio62";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi8_default: qup-spi8-default {
|
||||
pinmux {
|
||||
pins = "gpio42", "gpio43",
|
||||
|
|
@ -1635,6 +1708,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi8_cs_gpio: qup-spi8-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio42", "gpio43",
|
||||
"gpio44";
|
||||
function = "qup12";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio45";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi10_default: qup-spi10-default {
|
||||
pinmux {
|
||||
pins = "gpio86", "gpio87",
|
||||
|
|
@ -1643,6 +1729,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi10_cs_gpio: qup-spi10-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio86", "gpio87",
|
||||
"gpio88";
|
||||
function = "qup14";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio89";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_spi11_default: qup-spi11-default {
|
||||
pinmux {
|
||||
pins = "gpio53", "gpio54",
|
||||
|
|
@ -1651,6 +1750,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
qup_spi11_cs_gpio: qup-spi11-cs-gpio {
|
||||
pinmux {
|
||||
pins = "gpio53", "gpio54",
|
||||
"gpio55";
|
||||
function = "qup15";
|
||||
};
|
||||
|
||||
pinmux-cs {
|
||||
pins = "gpio56";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
qup_uart0_default: qup-uart0-default {
|
||||
pinmux {
|
||||
pins = "gpio34", "gpio35",
|
||||
|
|
@ -1742,6 +1854,45 @@
|
|||
};
|
||||
};
|
||||
|
||||
sec_mi2s_active: sec-mi2s-active {
|
||||
pinmux {
|
||||
pins = "gpio49", "gpio50", "gpio51";
|
||||
function = "mi2s_1";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio49", "gpio50", "gpio51";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pri_mi2s_active: pri-mi2s-active {
|
||||
pinmux {
|
||||
pins = "gpio53", "gpio54", "gpio55", "gpio56";
|
||||
function = "mi2s_0";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio53", "gpio54", "gpio55", "gpio56";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pri_mi2s_mclk_active: pri-mi2s-mclk-active {
|
||||
pinmux {
|
||||
pins = "gpio57";
|
||||
function = "lpass_ext";
|
||||
};
|
||||
|
||||
pinconf {
|
||||
pins = "gpio57";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdc1_on: sdc1-on {
|
||||
pinconf-clk {
|
||||
pins = "sdc1_clk";
|
||||
|
|
@ -1907,6 +2058,8 @@
|
|||
operating-points-v2 = <&gpu_opp_table>;
|
||||
qcom,gmu = <&gmu>;
|
||||
|
||||
#cooling-cells = <2>;
|
||||
|
||||
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "gfx-mem";
|
||||
|
||||
|
|
@ -1958,7 +2111,7 @@
|
|||
};
|
||||
|
||||
adreno_smmu: iommu@5040000 {
|
||||
compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
|
||||
compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
|
||||
reg = <0 0x05040000 0 0x10000>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <2>;
|
||||
|
|
@ -2792,6 +2945,18 @@
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
camcc: clock-controller@ad00000 {
|
||||
compatible = "qcom,sc7180-camcc";
|
||||
reg = <0 0x0ad00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_CAMERA_AHB_CLK>,
|
||||
<&gcc GCC_CAMERA_XO_CLK>;
|
||||
clock-names = "bi_tcxo", "iface", "xo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
mdss: mdss@ae00000 {
|
||||
compatible = "qcom,sc7180-mdss";
|
||||
reg = <0 0x0ae00000 0 0x1000>;
|
||||
|
|
@ -2811,7 +2976,7 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
|
|
@ -3389,6 +3554,36 @@
|
|||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
lpass_cpu: lpass@62f00000 {
|
||||
compatible = "qcom,sc7180-lpass-cpu";
|
||||
|
||||
reg = <0 0x62f00000 0 0x29000>;
|
||||
reg-names = "lpass-lpaif";
|
||||
|
||||
iommus = <&apps_smmu 0x1020 0>;
|
||||
|
||||
power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
|
||||
|
||||
clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
|
||||
<&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
|
||||
<&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
|
||||
<&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
|
||||
<&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
|
||||
<&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
|
||||
|
||||
clock-names = "pcnoc-sway-clk", "audio-core",
|
||||
"mclk0", "pcnoc-mport-clk",
|
||||
"mi2s-bit-clk0", "mi2s-bit-clk1";
|
||||
|
||||
|
||||
#sound-dai-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "lpass-irq-lpaif";
|
||||
};
|
||||
|
||||
lpass_hm: clock-controller@63000000 {
|
||||
compatible = "qcom,sc7180-lpasshm";
|
||||
reg = <0 0x63000000 0 0x28>;
|
||||
|
|
@ -3402,7 +3597,7 @@
|
|||
|
||||
thermal-zones {
|
||||
cpu0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 1>;
|
||||
|
|
@ -3451,7 +3646,7 @@
|
|||
};
|
||||
|
||||
cpu1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 2>;
|
||||
|
|
@ -3500,7 +3695,7 @@
|
|||
};
|
||||
|
||||
cpu2-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 3>;
|
||||
|
|
@ -3549,7 +3744,7 @@
|
|||
};
|
||||
|
||||
cpu3-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 4>;
|
||||
|
|
@ -3598,7 +3793,7 @@
|
|||
};
|
||||
|
||||
cpu4-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 5>;
|
||||
|
|
@ -3647,7 +3842,7 @@
|
|||
};
|
||||
|
||||
cpu5-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 6>;
|
||||
|
|
@ -3696,7 +3891,7 @@
|
|||
};
|
||||
|
||||
cpu6-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 9>;
|
||||
|
|
@ -3737,7 +3932,7 @@
|
|||
};
|
||||
|
||||
cpu7-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 10>;
|
||||
|
|
@ -3778,7 +3973,7 @@
|
|||
};
|
||||
|
||||
cpu8-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 11>;
|
||||
|
|
@ -3819,7 +4014,7 @@
|
|||
};
|
||||
|
||||
cpu9-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 12>;
|
||||
|
|
@ -3860,7 +4055,7 @@
|
|||
};
|
||||
|
||||
aoss0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 0>;
|
||||
|
|
@ -3881,7 +4076,7 @@
|
|||
};
|
||||
|
||||
cpuss0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 7>;
|
||||
|
|
@ -3901,7 +4096,7 @@
|
|||
};
|
||||
|
||||
cpuss1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 8>;
|
||||
|
|
@ -3921,16 +4116,16 @@
|
|||
};
|
||||
|
||||
gpuss0-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 13>;
|
||||
|
||||
trips {
|
||||
gpuss0_alert0: trip-point0 {
|
||||
temperature = <90000>;
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
gpuss0_crit: gpuss0_crit {
|
||||
|
|
@ -3939,19 +4134,26 @@
|
|||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss0_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpuss1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens0 14>;
|
||||
|
||||
trips {
|
||||
gpuss1_alert0: trip-point0 {
|
||||
temperature = <90000>;
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
gpuss1_crit: gpuss1_crit {
|
||||
|
|
@ -3960,10 +4162,17 @@
|
|||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&gpuss1_alert0>;
|
||||
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aoss1-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 0>;
|
||||
|
|
@ -3984,7 +4193,7 @@
|
|||
};
|
||||
|
||||
cwlan-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 1>;
|
||||
|
|
@ -4005,7 +4214,7 @@
|
|||
};
|
||||
|
||||
audio-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 2>;
|
||||
|
|
@ -4026,7 +4235,7 @@
|
|||
};
|
||||
|
||||
ddr-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 3>;
|
||||
|
|
@ -4047,7 +4256,7 @@
|
|||
};
|
||||
|
||||
q6-hvx-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 4>;
|
||||
|
|
@ -4068,7 +4277,7 @@
|
|||
};
|
||||
|
||||
camera-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 5>;
|
||||
|
|
@ -4089,7 +4298,7 @@
|
|||
};
|
||||
|
||||
mdm-core-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 6>;
|
||||
|
|
@ -4110,7 +4319,7 @@
|
|||
};
|
||||
|
||||
mdm-dsp-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 7>;
|
||||
|
|
@ -4131,7 +4340,7 @@
|
|||
};
|
||||
|
||||
npu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 8>;
|
||||
|
|
@ -4152,7 +4361,7 @@
|
|||
};
|
||||
|
||||
video-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <0>;
|
||||
|
||||
thermal-sensors = <&tsens1 9>;
|
||||
|
|
|
|||
|
|
@ -830,7 +830,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp1_dma: dma@c144000 {
|
||||
blsp1_dma: dma-controller@c144000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x0c144000 0x1f000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -944,7 +944,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
blsp2_dma: dma@c184000 {
|
||||
blsp2_dma: dma-controller@c184000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0x0c184000 0x1f000>;
|
||||
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -633,6 +633,15 @@ ap_ts_i2c: &i2c14 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Cheza fw does not properly program the GPU aperture to allow the
|
||||
* GPU to update the SMMU pagetables for context switches. Work
|
||||
* around this by dropping the "qcom,adreno-smmu" compat string.
|
||||
*/
|
||||
&adreno_smmu {
|
||||
compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
iommus = <&apps_smmu 0x781 0x0>,
|
||||
<&apps_smmu 0x724 0x3>;
|
||||
|
|
@ -644,10 +653,12 @@ ap_ts_i2c: &i2c14 {
|
|||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
iommus = <&apps_smmu 0x0 0x3>;
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
iommus = <&apps_smmu 0x6c0 0x3>;
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
|
|
|
|||
|
|
@ -1120,9 +1120,12 @@
|
|||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core";
|
||||
status = "disabled";
|
||||
|
||||
i2c0: i2c@880000 {
|
||||
|
|
@ -1137,6 +1140,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1150,6 +1157,9 @@
|
|||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1163,6 +1173,9 @@
|
|||
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1178,6 +1191,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1191,6 +1208,9 @@
|
|||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1204,6 +1224,9 @@
|
|||
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1219,6 +1242,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1232,6 +1259,9 @@
|
|||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1245,6 +1275,9 @@
|
|||
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1260,6 +1293,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1273,6 +1310,9 @@
|
|||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1286,6 +1326,9 @@
|
|||
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1301,6 +1344,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1314,6 +1361,9 @@
|
|||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1327,6 +1377,9 @@
|
|||
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1342,6 +1395,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1355,6 +1412,9 @@
|
|||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1368,6 +1428,9 @@
|
|||
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1383,6 +1446,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1396,6 +1463,9 @@
|
|||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1409,6 +1479,9 @@
|
|||
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1437,6 +1510,9 @@
|
|||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1450,6 +1526,9 @@
|
|||
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -1460,9 +1539,12 @@
|
|||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x6c3 0x0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core";
|
||||
status = "disabled";
|
||||
|
||||
i2c8: i2c@a80000 {
|
||||
|
|
@ -1477,6 +1559,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1490,6 +1576,9 @@
|
|||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1503,6 +1592,9 @@
|
|||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1518,6 +1610,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1531,6 +1627,9 @@
|
|||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1544,6 +1643,9 @@
|
|||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1559,6 +1661,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1572,6 +1678,9 @@
|
|||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1585,6 +1694,9 @@
|
|||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1600,6 +1712,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1613,6 +1729,9 @@
|
|||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1626,6 +1745,9 @@
|
|||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1641,6 +1763,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1654,6 +1780,9 @@
|
|||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1667,6 +1796,9 @@
|
|||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1682,6 +1814,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1695,6 +1831,9 @@
|
|||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1708,6 +1847,9 @@
|
|||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1723,6 +1865,10 @@
|
|||
#size-cells = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1736,6 +1882,9 @@
|
|||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1749,6 +1898,9 @@
|
|||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1765,6 +1917,10 @@
|
|||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
status = "disabled";
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
};
|
||||
|
||||
spi15: spi@a9c000 {
|
||||
|
|
@ -1777,6 +1933,9 @@
|
|||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -1790,6 +1949,9 @@
|
|||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&qup_opp_table>;
|
||||
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -2138,10 +2300,41 @@
|
|||
};
|
||||
};
|
||||
|
||||
cryptobam: dma@1dc4000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
reg = <0 0x01dc4000 0 0x24000>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rpmhcc 15>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
qcom,controlled-remotely = <1>;
|
||||
iommus = <&apps_smmu 0x704 0x1>,
|
||||
<&apps_smmu 0x706 0x1>,
|
||||
<&apps_smmu 0x714 0x1>,
|
||||
<&apps_smmu 0x716 0x1>;
|
||||
};
|
||||
|
||||
crypto: crypto@1dfa000 {
|
||||
compatible = "qcom,crypto-v5.4";
|
||||
reg = <0 0x01dfa000 0 0x6000>;
|
||||
clocks = <&gcc GCC_CE1_AHB_CLK>,
|
||||
<&gcc GCC_CE1_AHB_CLK>,
|
||||
<&rpmhcc 15>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
dmas = <&cryptobam 6>, <&cryptobam 7>;
|
||||
dma-names = "rx", "tx";
|
||||
iommus = <&apps_smmu 0x704 0x1>,
|
||||
<&apps_smmu 0x706 0x1>,
|
||||
<&apps_smmu 0x714 0x1>,
|
||||
<&apps_smmu 0x716 0x1>;
|
||||
};
|
||||
|
||||
ipa: ipa@1e40000 {
|
||||
compatible = "qcom,sdm845-ipa";
|
||||
|
||||
iommus = <&apps_smmu 0x720 0x3>;
|
||||
iommus = <&apps_smmu 0x720 0x0>,
|
||||
<&apps_smmu 0x722 0x0>;
|
||||
reg = <0 0x1e40000 0 0x7000>,
|
||||
<0 0x1e47000 0 0x2000>,
|
||||
<0 0x1e04000 0 0x2c000>;
|
||||
|
|
@ -2149,8 +2342,8 @@
|
|||
"ipa-shared",
|
||||
"gsi";
|
||||
|
||||
interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
||||
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
||||
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ipa",
|
||||
|
|
@ -3661,6 +3854,9 @@
|
|||
iommus = <&apps_smmu 0x10a0 0x8>,
|
||||
<&apps_smmu 0x10b0 0x0>;
|
||||
memory-region = <&venus_mem>;
|
||||
interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
|
||||
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
|
||||
interconnect-names = "video-mem", "cpu-cfg";
|
||||
|
||||
video-core0 {
|
||||
compatible = "venus-decoder";
|
||||
|
|
@ -4103,7 +4299,7 @@
|
|||
};
|
||||
|
||||
adreno_smmu: iommu@5040000 {
|
||||
compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
|
||||
compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
|
||||
reg = <0 0x5040000 0 0x10000>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <2>;
|
||||
|
|
@ -4484,7 +4680,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
slimbam: dma@17184000 {
|
||||
slimbam: dma-controller@17184000 {
|
||||
compatible = "qcom,bam-v1.7.0";
|
||||
qcom,controlled-remotely;
|
||||
reg = <0 0x17184000 0 0x2a000>;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/gpio-keys.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
#include <dt-bindings/sound/qcom,q6asm.h>
|
||||
|
|
@ -21,6 +23,47 @@
|
|||
aliases {
|
||||
hsuart0 = &uart6;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>;
|
||||
|
||||
lid {
|
||||
gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
wakeup-source;
|
||||
wakeup-event-action = <EV_ACT_DEASSERTED>;
|
||||
};
|
||||
|
||||
mode {
|
||||
gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_TABLET_MODE>;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "boe,nv133fhm-n61";
|
||||
no-hpd;
|
||||
|
||||
ports {
|
||||
port {
|
||||
panel_in_edp: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sn65dsi86_refclk: sn65dsi86-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
};
|
||||
|
||||
&adsp_pas {
|
||||
|
|
@ -232,16 +275,30 @@
|
|||
};
|
||||
};
|
||||
|
||||
&apps_smmu {
|
||||
/* TODO: Figure out how to survive booting with this enabled */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cdsp_pas {
|
||||
firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
vdda-supply = <&vreg_l26a_1p2>;
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in_a>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_phy {
|
||||
status = "okay";
|
||||
vdds-supply = <&vreg_l1a_0p875>;
|
||||
};
|
||||
|
||||
&gcc {
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
|
|
@ -264,23 +321,28 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@15 {
|
||||
tsel: hid@15 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x15>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
};
|
||||
|
||||
hid@2c {
|
||||
tsc2: hid@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x20>;
|
||||
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_hid_active>;
|
||||
pinctrl-0 = <&i2c3_hid_active>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -288,15 +350,54 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@10 {
|
||||
tsc1: hid@10 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x10>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_hid_active>;
|
||||
pinctrl-0 = <&i2c5_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
sn65dsi86: bridge@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sn65dsi86_pin_active>;
|
||||
|
||||
enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vpll-supply = <&vreg_l14a_1p88>;
|
||||
vccio-supply = <&vreg_l14a_1p88>;
|
||||
|
||||
clocks = <&sn65dsi86_refclk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
sn65dsi86_in_a: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
sn65dsi86_out: endpoint {
|
||||
remote-endpoint = <&panel_in_edp>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -304,7 +405,7 @@
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hid@5c {
|
||||
ecsh: hid@5c {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x5c>;
|
||||
hid-descr-addr = <0x1>;
|
||||
|
|
@ -312,14 +413,30 @@
|
|||
interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c12_hid_active>;
|
||||
pinctrl-0 = <&i2c11_hid_active>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mss_pil {
|
||||
firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn";
|
||||
};
|
||||
|
||||
&qup_i2c10_default {
|
||||
pinconf {
|
||||
pins = "gpio55", "gpio56";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&qup_i2c12_default {
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
|
|
@ -426,8 +543,14 @@
|
|||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <81 4>;
|
||||
|
||||
i2c2_hid_active: i2c2-hid-active {
|
||||
pins = <37>;
|
||||
sn65dsi86_pin_active: sn65dsi86-enable {
|
||||
pins = "gpio96";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
i2c3_hid_active: i2c2-hid-active {
|
||||
pins = "gpio37";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -435,8 +558,8 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c6_hid_active: i2c6-hid-active {
|
||||
pins = <125>;
|
||||
i2c5_hid_active: i2c5-hid-active {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -444,8 +567,8 @@
|
|||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
i2c12_hid_active: i2c12-hid-active {
|
||||
pins = <92>;
|
||||
i2c11_hid_active: i2c11-hid-active {
|
||||
pins = "gpio92";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
|
|
@ -454,13 +577,29 @@
|
|||
};
|
||||
|
||||
wcd_intr_default: wcd_intr_default {
|
||||
pins = <54>;
|
||||
pins = "gpio54";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
lid_pin_active: lid-pin {
|
||||
pins = "gpio124";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mode_pin_active: mode-pin {
|
||||
pins = "gpio95";
|
||||
function = "gpio";
|
||||
|
||||
input-enable;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,463 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "sm8150.dtsi"
|
||||
#include "pm8150.dtsi"
|
||||
#include "pm8150b.dtsi"
|
||||
#include "pm8150l.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8150 HDK";
|
||||
compatible = "qcom,sm8150-hdk", "qcom,sm8150";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: pm8150-s4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
vol-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8150-rpmh-regulators {
|
||||
compatible = "qcom,pm8150-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
|
||||
vdd-l2-l10-supply = <&vreg_bob>;
|
||||
vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
|
||||
vdd-l6-l9-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
|
||||
vdd-l13-l16-l17-supply = <&vreg_bob>;
|
||||
|
||||
vreg_s5a_2p0: smps5 {
|
||||
regulator-min-microvolt = <1904000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
};
|
||||
|
||||
vreg_s6a_0p9: smps6 {
|
||||
regulator-min-microvolt = <920000>;
|
||||
regulator-max-microvolt = <1128000>;
|
||||
};
|
||||
|
||||
vdda_wcss_pll:
|
||||
vreg_l1a_0p75: ldo1 {
|
||||
regulator-min-microvolt = <752000>;
|
||||
regulator-max-microvolt = <752000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdd_pdphy:
|
||||
vdda_usb_hs_3p1:
|
||||
vreg_l2a_3p1: ldo2 {
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3a_0p8: ldo3 {
|
||||
regulator-min-microvolt = <480000>;
|
||||
regulator-max-microvolt = <932000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdd_usb_hs_core:
|
||||
vdda_csi_0_0p9:
|
||||
vdda_csi_1_0p9:
|
||||
vdda_csi_2_0p9:
|
||||
vdda_csi_3_0p9:
|
||||
vdda_dsi_0_0p9:
|
||||
vdda_dsi_1_0p9:
|
||||
vdda_dsi_0_pll_0p9:
|
||||
vdda_dsi_1_pll_0p9:
|
||||
vdda_pcie_1ln_core:
|
||||
vdda_pcie_2ln_core:
|
||||
vdda_pll_hv_cc_ebi01:
|
||||
vdda_pll_hv_cc_ebi23:
|
||||
vdda_qrefs_0p875_5:
|
||||
vdda_sp_sensor:
|
||||
vdda_ufs_2ln_core_1:
|
||||
vdda_ufs_2ln_core_2:
|
||||
vdda_usb_ss_dp_core_1:
|
||||
vdda_usb_ss_dp_core_2:
|
||||
vdda_qlink_lv:
|
||||
vdda_qlink_lv_ck:
|
||||
vreg_l5a_0p875: ldo5 {
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6a_1p2: ldo6 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p8: ldo7 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vddpx_10:
|
||||
vreg_l9a_1p2: ldo9 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10a_2p5: ldo10 {
|
||||
regulator-min-microvolt = <2504000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11a_0p8: ldo11 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdd_qfprom:
|
||||
vdd_qfprom_sp:
|
||||
vdda_apc_cs_1p8:
|
||||
vdda_gfx_cs_1p8:
|
||||
vdda_usb_hs_1p8:
|
||||
vdda_qrefs_vref_1p8:
|
||||
vddpx_10_a:
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13a_2p7: ldo13 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2704000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p7: ldo15 {
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <1704000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16a_2p7: ldo16 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17a_3p0: ldo17 {
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8150l-rpmh-regulators {
|
||||
compatible = "qcom,pm8150l-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
|
||||
vdd-l1-l8-supply = <&vreg_s4a_1p8>;
|
||||
vdd-l2-l3-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l4-l5-l6-supply = <&vreg_bob>;
|
||||
vdd-l7-l11-supply = <&vreg_bob>;
|
||||
vdd-l9-l10-supply = <&vreg_bob>;
|
||||
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
vdd-flash-supply = <&vreg_bob>;
|
||||
vdd-rgb-supply = <&vreg_bob>;
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <4000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
|
||||
vreg_s8c_1p3: smps8 {
|
||||
regulator-min-microvolt = <1352000>;
|
||||
regulator-max-microvolt = <1352000>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdda_wcss_adcdac_1:
|
||||
vdda_wcss_adcdac_22:
|
||||
vreg_l2c_1p3: ldo2 {
|
||||
regulator-min-microvolt = <1304000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vdda_hv_ebi0:
|
||||
vdda_hv_ebi1:
|
||||
vdda_hv_ebi2:
|
||||
vdda_hv_ebi3:
|
||||
vdda_hv_refgen0:
|
||||
vdda_qlink_hv_ck:
|
||||
vreg_l3c_1p2: ldo3 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vddpx_5:
|
||||
vreg_l4c_1p8: ldo4 {
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <2928000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vddpx_6:
|
||||
vreg_l5c_1p8: ldo5 {
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <2928000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vddpx_2:
|
||||
vreg_l6c_2p9: ldo6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_3p0: ldo7 {
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p9: ldo9 {
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10c_3p3: ldo10 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11c_3p3: ldo11 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8009-rpmh-regulators {
|
||||
compatible = "qcom,pm8009-rpmh-regulators";
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vreg_bob>;
|
||||
|
||||
vdd-l2-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l5-l6-supply = <&vreg_bob>;
|
||||
|
||||
vreg_l2f_1p2: ldo2 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5f_2p85: ldo5 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6f_2p85: ldo6 {
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <2856000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon {
|
||||
pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
resin {
|
||||
compatible = "qcom,pm8941-resin";
|
||||
interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "qcom/sm8150/adsp.mbn";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "qcom/sm8150/cdsp.mbn";
|
||||
};
|
||||
|
||||
&remoteproc_slpi {
|
||||
status = "okay";
|
||||
|
||||
firmware-name = "qcom/sm8150/slpi.mbn";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <0 4>, <126 4>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
|
||||
|
||||
vcc-supply = <&vreg_l10a_2p5>;
|
||||
vcc-max-microamp = <750000>;
|
||||
vccq-supply = <&vreg_l9a_1p2>;
|
||||
vccq-max-microamp = <700000>;
|
||||
vccq2-supply = <&vreg_s4a_1p8>;
|
||||
vccq2-max-microamp = <750000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
|
||||
vdda-max-microamp = <90200>;
|
||||
vdda-pll-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-max-microamp = <19000>;
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
vdda-pll-supply = <&vdd_usb_hs_core>;
|
||||
vdda33-supply = <&vdda_usb_hs_3p1>;
|
||||
vdda18-supply = <&vdda_usb_hs_1p8>;
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
status = "okay";
|
||||
vdda-pll-supply = <&vdd_usb_hs_core>;
|
||||
vdda33-supply = <&vdda_usb_hs_3p1>;
|
||||
vdda18-supply = <&vdda_usb_hs_1p8>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
|
||||
};
|
||||
|
||||
&usb_2_qmpphy {
|
||||
status = "okay";
|
||||
vdda-phy-supply = <&vreg_l3c_1p2>;
|
||||
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -369,14 +369,22 @@
|
|||
|
||||
&remoteproc_adsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8150/adsp.mdt";
|
||||
};
|
||||
|
||||
&remoteproc_cdsp {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8150/cdsp.mdt";
|
||||
};
|
||||
|
||||
&remoteproc_mpss {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8150/modem.mdt";
|
||||
};
|
||||
|
||||
&remoteproc_slpi {
|
||||
status = "okay";
|
||||
firmware-name = "qcom/sm8150/slpi.mdt";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
|
|
@ -429,3 +437,12 @@
|
|||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
|
||||
vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>;
|
||||
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
|
||||
vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>;
|
||||
vdd-3.3-ch0-supply = <&vreg_l11c_3p3>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -490,6 +490,13 @@
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
system-cache-controller@9200000 {
|
||||
compatible = "qcom,sm8150-llcc";
|
||||
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ufs_mem_hc: ufshc@1d84000 {
|
||||
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
|
||||
"jedec,ufs-2.0";
|
||||
|
|
@ -502,6 +509,8 @@
|
|||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
iommus = <&apps_smmu 0x300 0>;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
|
|
@ -789,6 +798,597 @@
|
|||
};
|
||||
};
|
||||
|
||||
stm@6002000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x06002000 0 0x1000>,
|
||||
<0 0x16280000 0 0x180000>;
|
||||
reg-names = "stm-base", "stm-stimulus-base";
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
stm_out: endpoint {
|
||||
remote-endpoint = <&funnel0_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6041000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06041000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel0_out: endpoint {
|
||||
remote-endpoint = <&merge_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
funnel0_in7: endpoint {
|
||||
remote-endpoint = <&stm_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6042000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06042000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel1_out: endpoint {
|
||||
remote-endpoint = <&merge_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
funnel1_in4: endpoint {
|
||||
remote-endpoint = <&swao_replicator_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6043000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06043000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel2_out: endpoint {
|
||||
remote-endpoint = <&merge_funnel_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel2_in2: endpoint {
|
||||
remote-endpoint = <&apss_merge_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6045000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06045000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
merge_funnel_out: endpoint {
|
||||
remote-endpoint = <&etf_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
merge_funnel_in0: endpoint {
|
||||
remote-endpoint = <&funnel0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
merge_funnel_in1: endpoint {
|
||||
remote-endpoint = <&funnel1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
merge_funnel_in2: endpoint {
|
||||
remote-endpoint = <&funnel2_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@6046000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x06046000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
replicator_out0: endpoint {
|
||||
remote-endpoint = <&etr_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator_out1: endpoint {
|
||||
remote-endpoint = <&replicator1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
replicator_in0: endpoint {
|
||||
remote-endpoint = <&etf_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etf@6047000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x06047000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etf_out: endpoint {
|
||||
remote-endpoint = <&replicator_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etf_in: endpoint {
|
||||
remote-endpoint = <&merge_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etr@6048000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x06048000 0 0x1000>;
|
||||
iommus = <&apps_smmu 0x05e0 0x0>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,scatter-gather;
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etr_in: endpoint {
|
||||
remote-endpoint = <&replicator_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@604a000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x0604a000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator1_out: endpoint {
|
||||
remote-endpoint = <&swao_funnel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
replicator1_in: endpoint {
|
||||
remote-endpoint = <&replicator_out1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@6b08000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x06b08000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
swao_funnel_out: endpoint {
|
||||
remote-endpoint = <&swao_etf_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
swao_funnel_in: endpoint {
|
||||
remote-endpoint = <&replicator1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etf@6b09000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x06b09000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
swao_etf_out: endpoint {
|
||||
remote-endpoint = <&swao_replicator_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
swao_etf_in: endpoint {
|
||||
remote-endpoint = <&swao_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
replicator@6b0a000 {
|
||||
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
|
||||
reg = <0 0x06b0a000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
qcom,replicator-loses-context;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
swao_replicator_out: endpoint {
|
||||
remote-endpoint = <&funnel1_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
swao_replicator_in: endpoint {
|
||||
remote-endpoint = <&swao_etf_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07040000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU0>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07140000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU1>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07240000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU2>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07340000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU3>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7440000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07440000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU4>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7540000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07540000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU5>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7640000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07640000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU6>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@7740000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x07740000 0 0x1000>;
|
||||
|
||||
cpu = <&CPU7>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
arm,coresight-loses-context-with-cpu;
|
||||
qcom,skip-power-up;
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint = <&apss_funnel_in7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@7800000 { /* APSS Funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x07800000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
apss_funnel_out: endpoint {
|
||||
remote-endpoint = <&apss_merge_funnel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
apss_funnel_in0: endpoint {
|
||||
remote-endpoint = <&etm0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
apss_funnel_in1: endpoint {
|
||||
remote-endpoint = <&etm1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
apss_funnel_in2: endpoint {
|
||||
remote-endpoint = <&etm2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
apss_funnel_in3: endpoint {
|
||||
remote-endpoint = <&etm3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
apss_funnel_in4: endpoint {
|
||||
remote-endpoint = <&etm4_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
apss_funnel_in5: endpoint {
|
||||
remote-endpoint = <&etm5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
apss_funnel_in6: endpoint {
|
||||
remote-endpoint = <&etm6_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
apss_funnel_in7: endpoint {
|
||||
remote-endpoint = <&etm7_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
funnel@7810000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x07810000 0 0x1000>;
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
apss_merge_funnel_out: endpoint {
|
||||
remote-endpoint = <&funnel2_in2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
apss_merge_funnel_in: endpoint {
|
||||
remote-endpoint = <&apss_funnel_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
remoteproc_cdsp: remoteproc@8300000 {
|
||||
compatible = "qcom,sm8150-cdsp-pas";
|
||||
reg = <0x0 0x08300000 0x0 0x4040>;
|
||||
|
|
@ -836,6 +1436,19 @@
|
|||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
};
|
||||
|
||||
usb_2_hsphy: phy@88e3000 {
|
||||
compatible = "qcom,sm8150-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-7nm-phy";
|
||||
reg = <0 0x088e3000 0 0x400>;
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
};
|
||||
|
||||
usb_1_qmpphy: phy@88e9000 {
|
||||
compatible = "qcom,sm8150-qmp-usb3-phy";
|
||||
reg = <0 0x088e9000 0 0x18c>,
|
||||
|
|
@ -885,6 +1498,37 @@
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
usb_2_qmpphy: phy@88eb000 {
|
||||
compatible = "qcom,sm8150-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x200>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
|
||||
|
||||
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
|
||||
<&gcc GCC_USB3_PHY_SEC_BCR>;
|
||||
reset-names = "phy", "common";
|
||||
|
||||
usb_2_ssphy: lane@88eb200 {
|
||||
reg = <0 0x088eb200 0 0x200>,
|
||||
<0 0x088eb400 0 0x200>,
|
||||
<0 0x088eb800 0 0x800>,
|
||||
<0 0x088eb600 0 0x200>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
clock-output-names = "usb3_uni_phy_pipe_clk_src";
|
||||
};
|
||||
};
|
||||
|
||||
usb_1: usb@a6f8800 {
|
||||
compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
|
|
@ -922,6 +1566,7 @@
|
|||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x140 0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
|
||||
|
|
@ -929,6 +1574,51 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb_2: usb@a8f8800 {
|
||||
compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a8f8800 0 0x400>;
|
||||
status = "disabled";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||||
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
|
||||
"sleep", "xo";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hs_phy_irq", "ss_phy_irq",
|
||||
"dm_hs_phy_irq", "dp_hs_phy_irq";
|
||||
|
||||
power-domains = <&gcc USB30_SEC_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
usb_2_dwc3: dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x160 0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
};
|
||||
|
||||
camnoc_virt: interconnect@ac00000 {
|
||||
compatible = "qcom,sm8150-camnoc-virt";
|
||||
reg = <0 0x0ac00000 0 0x1000>;
|
||||
|
|
@ -987,6 +1677,94 @@
|
|||
cell-index = <0>;
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
|
||||
reg = <0 0x15000000 0 0x100000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
remoteproc_adsp: remoteproc@17300000 {
|
||||
compatible = "qcom,sm8150-adsp-pas";
|
||||
reg = <0x0 0x17300000 0x0 0x4040>;
|
||||
|
|
@ -1206,6 +1984,29 @@
|
|||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
|
||||
wifi: wifi@18800000 {
|
||||
compatible = "qcom,wcn3990-wifi";
|
||||
reg = <0 0x18800000 0 0x800000>;
|
||||
reg-names = "membase";
|
||||
memory-region = <&wlan_mem>;
|
||||
clock-names = "cxo_ref_clk_pin", "qdss";
|
||||
clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
|
||||
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x0640 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,454 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "sm8250.dtsi"
|
||||
#include "pm8150.dtsi"
|
||||
#include "pm8150b.dtsi"
|
||||
#include "pm8150l.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8250 HDK";
|
||||
compatible = "qcom,sm8250-hdk", "qcom,sm8250";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart12;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vph_pwr: vph-pwr-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vph_pwr";
|
||||
regulator-min-microvolt = <3700000>;
|
||||
regulator-max-microvolt = <3700000>;
|
||||
};
|
||||
|
||||
vreg_s4a_1p8: pm8150-s4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s4a_1p8";
|
||||
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
vreg_s6c_0p88: smpc6-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_s6c_0p88";
|
||||
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vph_pwr>;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
vol-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&apps_rsc {
|
||||
pm8150-rpmh-regulators {
|
||||
compatible = "qcom,pm8150-rpmh-regulators";
|
||||
qcom,pmic-id = "a";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-s9-supply = <&vph_pwr>;
|
||||
vdd-s10-supply = <&vph_pwr>;
|
||||
vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>;
|
||||
vdd-l2-l10-supply = <&vreg_bob>;
|
||||
vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>;
|
||||
vdd-l6-l9-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
|
||||
vdd-l13-l16-l17-supply = <&vreg_bob>;
|
||||
|
||||
vreg_s5a_1p9: smps5 {
|
||||
regulator-name = "vreg_s5a_1p9";
|
||||
regulator-min-microvolt = <1824000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_s6a_0p95: smps6 {
|
||||
regulator-name = "vreg_s6a_0p95";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1128000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2a_3p1: ldo2 {
|
||||
regulator-name = "vreg_l2a_3p1";
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3a_0p9: ldo3 {
|
||||
regulator-name = "vreg_l3a_0p9";
|
||||
regulator-min-microvolt = <928000>;
|
||||
regulator-max-microvolt = <932000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5a_0p88: ldo5 {
|
||||
regulator-name = "vreg_l5a_0p88";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6a_1p2: ldo6 {
|
||||
regulator-name = "vreg_l6a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7a_1p7: ldo7 {
|
||||
regulator-name = "vreg_l7a_1p7";
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9a_1p2: ldo9 {
|
||||
regulator-name = "vreg_l9a_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10a_1p8: ldo10 {
|
||||
regulator-name = "vreg_l10a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l12a_1p8: ldo12 {
|
||||
regulator-name = "vreg_l12a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l13a_ts_3p0: ldo13 {
|
||||
regulator-name = "vreg_l13a_ts_3p0";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l14a_1p8: ldo14 {
|
||||
regulator-name = "vreg_l14a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l15a_1p8: ldo15 {
|
||||
regulator-name = "vreg_l15a_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l16a_3p3: ldo16 {
|
||||
regulator-name = "vreg_l16a_3p3";
|
||||
regulator-min-microvolt = <3024000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l17a_2p96: ldo17 {
|
||||
regulator-name = "vreg_l17a_2p96";
|
||||
regulator-min-microvolt = <2496000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l18a_0p92: ldo18 {
|
||||
regulator-name = "vreg_l18a_0p92";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8150l-rpmh-regulators {
|
||||
compatible = "qcom,pm8150l-rpmh-regulators";
|
||||
qcom,pmic-id = "c";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
vdd-s3-supply = <&vph_pwr>;
|
||||
vdd-s4-supply = <&vph_pwr>;
|
||||
vdd-s5-supply = <&vph_pwr>;
|
||||
vdd-s6-supply = <&vph_pwr>;
|
||||
vdd-s7-supply = <&vph_pwr>;
|
||||
vdd-s8-supply = <&vph_pwr>;
|
||||
vdd-l1-l8-supply = <&vreg_s4a_1p8>;
|
||||
vdd-l2-l3-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l4-l5-l6-supply = <&vreg_bob>;
|
||||
vdd-l7-l11-supply = <&vreg_bob>;
|
||||
vdd-l9-l10-supply = <&vreg_bob>;
|
||||
vdd-bob-supply = <&vph_pwr>;
|
||||
|
||||
vreg_bob: bob {
|
||||
regulator-name = "vreg_bob";
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
|
||||
vreg_s8c_1p3: smps8 {
|
||||
regulator-name = "vreg_s8c_1p3";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l1c_1p8: ldo1 {
|
||||
regulator-name = "vreg_l1c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2c_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2c_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3c_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3c_0p8";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l4c_1p8: ldo4 {
|
||||
regulator-name = "vreg_l4c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5c_1p8: ldo5 {
|
||||
regulator-name = "vreg_l5c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6c_2p96: ldo6 {
|
||||
regulator-name = "vreg_l6c_2p96";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7c_cam_vcm0_2p85: ldo7 {
|
||||
regulator-name = "vreg_l7c_cam_vcm0_2p85";
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l8c_1p8: ldo8 {
|
||||
regulator-name = "vreg_l8c_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l9c_2p96: ldo9 {
|
||||
regulator-name = "vreg_l9c_2p96";
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l10c_3p0: ldo10 {
|
||||
regulator-name = "vreg_l10c_3p0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l11c_3p3: ldo11 {
|
||||
regulator-name = "vreg_l11c_3p3";
|
||||
regulator-min-microvolt = <3104000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
pm8009-rpmh-regulators {
|
||||
compatible = "qcom,pm8009-rpmh-regulators";
|
||||
qcom,pmic-id = "f";
|
||||
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vreg_bob>;
|
||||
vdd-l2-supply = <&vreg_s8c_1p3>;
|
||||
vdd-l5-l6-supply = <&vreg_bob>;
|
||||
vdd-l7-supply = <&vreg_s4a_1p8>;
|
||||
|
||||
vreg_l1f_cam_dvdd1_1p1: ldo1 {
|
||||
regulator-name = "vreg_l1f_cam_dvdd1_1p1";
|
||||
regulator-min-microvolt = <1104000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l2f_cam_dvdd0_1p2: ldo2 {
|
||||
regulator-name = "vreg_l2f_cam_dvdd0_1p2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l3f_cam_dvdd2_1p05: ldo3 {
|
||||
regulator-name = "vreg_l3f_cam_dvdd2_1p05";
|
||||
regulator-min-microvolt = <1056000>;
|
||||
regulator-max-microvolt = <1056000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l5f_cam_avdd0_2p85: ldo5 {
|
||||
regulator-name = "vreg_l5f_cam_avdd0_2p85";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l6f_cam_avdd1_2p8: ldo6 {
|
||||
regulator-name = "vreg_l6f_cam_avdd1_2p8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
|
||||
vreg_l7f_1p8: ldo7 {
|
||||
regulator-name = "vreg_l7f_1p8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_id_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pon {
|
||||
pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
resin {
|
||||
compatible = "qcom,pm8941-resin";
|
||||
interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
|
||||
debounce = <15625>;
|
||||
bias-pull-up;
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
gpio-reserved-ranges = <28 4>, <40 4>;
|
||||
};
|
||||
|
||||
&uart12 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ufs_mem_hc {
|
||||
status = "okay";
|
||||
|
||||
vcc-supply = <&vreg_l17a_2p96>;
|
||||
vcc-max-microamp = <800000>;
|
||||
vccq-supply = <&vreg_l6a_1p2>;
|
||||
vccq-max-microamp = <800000>;
|
||||
vccq2-supply = <&vreg_s4a_1p8>;
|
||||
vccq2-max-microamp = <800000>;
|
||||
};
|
||||
|
||||
&ufs_mem_phy {
|
||||
status = "okay";
|
||||
|
||||
vdda-phy-supply = <&vreg_l5a_0p88>;
|
||||
vdda-max-microamp = <89900>;
|
||||
vdda-pll-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-max-microamp = <18800>;
|
||||
};
|
||||
|
||||
&usb_1_hsphy {
|
||||
status = "okay";
|
||||
vdda-pll-supply = <&vreg_l5a_0p88>;
|
||||
vdda33-supply = <&vreg_l2a_3p1>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
};
|
||||
|
||||
&usb_2_hsphy {
|
||||
status = "okay";
|
||||
vdda-pll-supply = <&vreg_l5a_0p88>;
|
||||
vdda33-supply = <&vreg_l2a_3p1>;
|
||||
vdda18-supply = <&vreg_l12a_1p8>;
|
||||
};
|
||||
|
||||
&usb_1_qmpphy {
|
||||
status = "okay";
|
||||
vdda-phy-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l18a_0p92>;
|
||||
};
|
||||
|
||||
&usb_2_qmpphy {
|
||||
status = "okay";
|
||||
vdda-phy-supply = <&vreg_l9a_1p2>;
|
||||
vdda-pll-supply = <&vreg_l18a_0p92>;
|
||||
};
|
||||
|
||||
&usb_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_1_dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
|
||||
&usb_2_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SM8250 MTP";
|
||||
compatible = "qcom,sm8250-mtp";
|
||||
compatible = "qcom,sm8250-mtp", "qcom,sm8250";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart12;
|
||||
|
|
@ -378,6 +378,10 @@
|
|||
/* rtc6226 @ 64 */
|
||||
};
|
||||
|
||||
&pm8150_rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qupv3_id_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -93,10 +93,10 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -110,8 +110,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -124,8 +124,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -138,8 +138,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
#cooling-cells = <2>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -152,8 +152,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -166,8 +166,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -181,8 +181,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
#cooling-cells = <2>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -195,8 +195,8 @@
|
|||
qcom,freq-domain = <&cpufreq_hw 2>;
|
||||
#cooling-cells = <2>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -429,6 +429,13 @@
|
|||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
rng: rng@793000 {
|
||||
compatible = "qcom,prng-ee";
|
||||
reg = <0 0x00793000 0 0x1000>;
|
||||
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
||||
clock-names = "core";
|
||||
};
|
||||
|
||||
qup_opp_table: qup-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
|
|
@ -456,6 +463,7 @@
|
|||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
iommus = <&apps_smmu 0x63 0x0>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -662,6 +670,7 @@
|
|||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
iommus = <&apps_smmu 0x5a3 0x0>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -924,6 +933,7 @@
|
|||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
iommus = <&apps_smmu 0x43 0x0>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -1172,6 +1182,8 @@
|
|||
|
||||
power-domains = <&gcc UFS_PHY_GDSC>;
|
||||
|
||||
iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
|
|
@ -1417,8 +1429,35 @@
|
|||
mboxes = <&ipcc IPCC_CLIENT_SLPI
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
label = "lpass";
|
||||
label = "slpi";
|
||||
qcom,remote-pid = <3>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "sdsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x0541 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x0542 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x0543 0x0>;
|
||||
/* note: shared-cb = <4> in downstream */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1455,8 +1494,201 @@
|
|||
mboxes = <&ipcc IPCC_CLIENT_CDSP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
|
||||
label = "lpass";
|
||||
label = "cdsp";
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "cdsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x1001 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x1002 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1003 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1004 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1005 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x1006 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x1007 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x1008 0x0460>;
|
||||
};
|
||||
|
||||
/* note: secure cb9 in downstream */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb_1_hsphy: phy@88e3000 {
|
||||
compatible = "qcom,sm8250-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-7nm-phy";
|
||||
reg = <0 0x088e3000 0 0x400>;
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
};
|
||||
|
||||
usb_2_hsphy: phy@88e4000 {
|
||||
compatible = "qcom,sm8250-usb-hs-phy",
|
||||
"qcom,usb-snps-hs-7nm-phy";
|
||||
reg = <0 0x088e4000 0 0x400>;
|
||||
status = "disabled";
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "ref";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
};
|
||||
|
||||
usb_1_qmpphy: phy@88e9000 {
|
||||
compatible = "qcom,sm8250-qmp-usb3-phy";
|
||||
reg = <0 0x088e9000 0 0x200>,
|
||||
<0 0x088e8000 0 0x20>;
|
||||
reg-names = "reg-base", "dp_com";
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux", "ref_clk_src", "com_aux";
|
||||
|
||||
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
||||
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
||||
reset-names = "phy", "common";
|
||||
|
||||
usb_1_ssphy: lanes@88e9200 {
|
||||
reg = <0 0x088e9200 0 0x200>,
|
||||
<0 0x088e9400 0 0x200>,
|
||||
<0 0x088e9c00 0 0x400>,
|
||||
<0 0x088e9600 0 0x200>,
|
||||
<0 0x088e9800 0 0x200>,
|
||||
<0 0x088e9a00 0 0x100>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
clock-output-names = "usb3_phy_pipe_clk_src";
|
||||
};
|
||||
};
|
||||
|
||||
usb_2_qmpphy: phy@88eb000 {
|
||||
compatible = "qcom,sm8250-qmp-usb3-uni-phy";
|
||||
reg = <0 0x088eb000 0 0x200>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
|
||||
|
||||
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
|
||||
<&gcc GCC_USB3_PHY_SEC_BCR>;
|
||||
reset-names = "phy", "common";
|
||||
|
||||
usb_2_ssphy: lane@88eb200 {
|
||||
reg = <0 0x088eb200 0 0x200>,
|
||||
<0 0x088eb400 0 0x200>,
|
||||
<0 0x088eb800 0 0x800>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "pipe0";
|
||||
clock-output-names = "usb3_uni_phy_pipe_clk_src";
|
||||
};
|
||||
};
|
||||
|
||||
sdhc_2: sdhci@8804000 {
|
||||
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
|
||||
reg = <0 0x08804000 0 0x1000>;
|
||||
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hc_irq", "pwr_irq";
|
||||
|
||||
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
||||
<&gcc GCC_SDCC2_APPS_CLK>,
|
||||
<&xo_board>;
|
||||
clock-names = "iface", "core", "xo";
|
||||
iommus = <&apps_smmu 0x4a0 0x0>;
|
||||
qcom,dll-config = <0x0007642c>;
|
||||
qcom,ddr-config = <0x80040868>;
|
||||
power-domains = <&rpmhpd SM8250_CX>;
|
||||
operating-points-v2 = <&sdhc2_opp_table>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
sdhc2_opp_table: sdhc2-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-19200000 {
|
||||
opp-hz = /bits/ 64 <19200000>;
|
||||
required-opps = <&rpmhpd_opp_min_svs>;
|
||||
};
|
||||
|
||||
opp-50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-202000000 {
|
||||
opp-hz = /bits/ 64 <202000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1481,6 +1713,96 @@
|
|||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
usb_1: usb@a6f8800 {
|
||||
compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a6f8800 0 0x400>;
|
||||
status = "disabled";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_EN>;
|
||||
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
|
||||
"sleep", "xo";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq", "ss_phy_irq";
|
||||
|
||||
power-domains = <&gcc USB30_PRIM_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
usb_1_dwc3: dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xcd00>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x0 0x0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
};
|
||||
|
||||
usb_2: usb@a8f8800 {
|
||||
compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
|
||||
reg = <0 0x0a8f8800 0 0x400>;
|
||||
status = "disabled";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_EN>;
|
||||
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
|
||||
"sleep", "xo";
|
||||
|
||||
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
||||
assigned-clock-rates = <19200000>, <200000000>;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
|
||||
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq", "ss_phy_irq";
|
||||
|
||||
power-domains = <&gcc USB30_SEC_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
|
||||
usb_2_dwc3: dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a800000 0 0xcd00>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&apps_smmu 0x20 0>;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_enblslpm_quirk;
|
||||
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,sm8250-pdc", "qcom,pdc";
|
||||
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
|
||||
|
|
@ -2156,6 +2478,111 @@
|
|||
};
|
||||
};
|
||||
|
||||
apps_smmu: iommu@15000000 {
|
||||
compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
|
||||
reg = <0 0x15000000 0 0x100000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <2>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
adsp: remoteproc@17300000 {
|
||||
compatible = "qcom,sm8250-adsp-pas";
|
||||
reg = <0 0x17300000 0 0x100>;
|
||||
|
|
@ -2192,6 +2619,32 @@
|
|||
|
||||
label = "lpass";
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
fastrpc {
|
||||
compatible = "qcom,fastrpc";
|
||||
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
||||
label = "adsp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x1803 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x1804 0x0>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x1805 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -177,6 +177,7 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
|
|||
|
||||
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
|
||||
&bcm_sn9,
|
||||
&bcm_qup0,
|
||||
};
|
||||
|
||||
static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
||||
|
|
@ -190,6 +191,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = {
|
|||
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
|
||||
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
|
||||
[SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
|
||||
[MASTER_QUP_1] = &qhm_qup1,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sdm845_aggre1_noc = {
|
||||
|
|
@ -218,6 +220,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = {
|
|||
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
|
||||
[SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
|
||||
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
|
||||
[MASTER_QUP_2] = &qhm_qup2,
|
||||
};
|
||||
|
||||
static const struct qcom_icc_desc sdm845_aggre2_noc = {
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#define SLAVE_A1NOC_SNOC 7
|
||||
#define SLAVE_SERVICE_A1NOC 8
|
||||
#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9
|
||||
#define MASTER_QUP_1 10
|
||||
|
||||
#define MASTER_A2NOC_CFG 0
|
||||
#define MASTER_QDSS_BAM 1
|
||||
|
|
@ -32,6 +33,7 @@
|
|||
#define SLAVE_A2NOC_SNOC 9
|
||||
#define SLAVE_ANOC_PCIE_SNOC 10
|
||||
#define SLAVE_SERVICE_A2NOC 11
|
||||
#define MASTER_QUP_2 12
|
||||
|
||||
#define MASTER_SPDM 0
|
||||
#define MASTER_TIC 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue