bnx2x: revised link register access
This is a semantic change, cleaning some sections in which the bnx2x handles the phy's registers. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Yaniv Rosner <yaniv.rosner@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
parent
1440090111
commit
a351d497f3
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@ -3754,44 +3754,35 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
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static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars) {
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u16 val16 = 0, lane, bam37 = 0;
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u16 val16 = 0, lane, i;
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struct bnx2x *bp = params->bp;
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static struct bnx2x_reg_set reg_set[] = {
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
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{MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff},
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{MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555},
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{MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
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/* Disable Autoneg: re-enable it after adv is done. */
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{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}
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};
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DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
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/* Set to default registers that may be overriden by 10G force */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
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MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_RX66_CONTROL, 0x7415);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
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/* Disable Autoneg: re-enable it after adv is done. */
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
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for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++)
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bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
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reg_set[i].val);
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/* Check adding advertisement for 1G KX */
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if (((vars->line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
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(vars->line_speed == SPEED_1000)) {
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u16 sd_digital;
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u32 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
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val16 |= (1<<5);
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/* Enable CL37 1G Parallel Detect */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
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(sd_digital | 0x1));
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
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DP(NETIF_MSG_LINK, "Advertize 1G\n");
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}
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if (((vars->line_speed == SPEED_AUTO_NEG) &&
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@ -3801,7 +3792,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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val16 |= (1<<7);
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/* Enable 10G Parallel Detect */
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
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MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
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DP(NETIF_MSG_LINK, "Advertize 10G\n");
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}
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@ -3835,10 +3826,9 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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offsetof(struct shmem_region, dev_info.
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port_hw_config[params->port].default_cfg)) &
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PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
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1);
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DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
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}
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@ -3852,11 +3842,8 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
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DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
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vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
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}
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL5_MISC7, &val16);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
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/* Over 1G - AN local device user page 1 */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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@ -3873,50 +3860,35 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u16 val;
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/* Disable Autoneg */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
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MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL3_UP1, 0x1);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
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/* Disable CL36 PCS Tx */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
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/* Double Wide Single Data Rate @ pll rate */
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
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/* Leave cl72 training enable, needed for KR */
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
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u16 i;
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static struct bnx2x_reg_set reg_set[] = {
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/* Disable Autoneg */
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
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{MDIO_AN_DEVAD, MDIO_WC_REG_PAR_DET_10G_CTRL, 0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
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0x3f00},
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{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
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{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
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{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
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/* Disable CL36 PCS Tx */
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{MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0},
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/* Double Wide Single Data Rate @ pll rate */
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{MDIO_WC_DEVAD, MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF},
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/* Leave cl72 training enable, needed for KR */
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{MDIO_PMA_DEVAD,
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MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
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0x2);
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0x2}
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};
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for (i = 0; i < sizeof(reg_set)/sizeof(struct bnx2x_reg_set); i++)
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bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
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reg_set[i].val);
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/* Leave CL72 enabled */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
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&val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
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val | 0x3800);
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
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0x3800);
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/* Set speed via PMA/PMD register */
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
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@ -3952,16 +3924,12 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
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struct bnx2x *bp = params->bp;
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u16 misc1_val, tap_val, tx_driver_val, lane, val;
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/* Hold rxSeqStart */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
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/* Hold tx_fifo_reset */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
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/* Disable CL73 AN */
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
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@ -3973,10 +3941,8 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
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MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
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/* Disable 100FX Idle detect */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_FX100_CTRL3, &val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_FX100_CTRL3, 0x0080);
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/* Set Block address to Remote PHY & Clear forced_speed[5] */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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@ -4037,16 +4003,12 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
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tx_driver_val);
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/* Enable fiber mode, enable and invert sig_det */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
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/* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL4_MISC3, &val);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
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/* Enable LPI pass through */
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DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
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@ -4244,40 +4206,35 @@ static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
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u16 lane)
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{
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struct bnx2x *bp = params->bp;
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u16 val16;
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u16 i;
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static struct bnx2x_reg_set wc_regs[] = {
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{MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
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{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
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{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
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{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
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0x0195},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
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0x0007},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
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0x0002},
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{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
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{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
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{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
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{MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
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};
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/* Set XFI clock comp as default. */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_RX66_CONTROL, &val16);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
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bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_RX66_CONTROL, (3<<13));
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for (i = 0; i < sizeof(wc_regs)/sizeof(struct bnx2x_reg_set); i++)
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bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
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wc_regs[i].val);
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bnx2x_warpcore_reset_lane(bp, phy, 1);
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bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_FX100_CTRL1, 0x014a);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_FX100_CTRL3, 0x0800);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
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lane = bnx2x_get_warpcore_lane(phy, params);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_TX_FIR_TAP, 0x0000);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
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bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
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MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
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bnx2x_warpcore_reset_lane(bp, phy, 0);
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}
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static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
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@ -4605,12 +4562,9 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
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CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
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MDIO_AER_BLOCK_AER_REG, 0);
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/* Enable 1G MDIO (1-copy) */
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bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
|
||||
&val16);
|
||||
bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
|
||||
val16 | 0x10);
|
||||
bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
|
||||
0x10);
|
||||
/* Set 1G loopback based on lane (1-copy) */
|
||||
lane = bnx2x_get_warpcore_lane(phy, params);
|
||||
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
|
||||
|
|
@ -4623,16 +4577,12 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
|
|||
bnx2x_set_aer_mmd(params, phy);
|
||||
} else {
|
||||
/* 10G & 20G */
|
||||
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
|
||||
bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
|
||||
0x4000);
|
||||
bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
|
||||
0x4000);
|
||||
|
||||
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
|
||||
bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
|
||||
bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
|
||||
MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -10819,7 +10769,7 @@ static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
|
|||
|
||||
/* Get speed operation status */
|
||||
bnx2x_cl22_read(bp, phy,
|
||||
0x19,
|
||||
MDIO_REG_GPHY_AUX_STATUS,
|
||||
&legacy_status);
|
||||
DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
|
||||
|
||||
|
|
|
|||
|
|
@ -125,6 +125,11 @@ typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
|
|||
struct link_params *params, u8 mode);
|
||||
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
|
||||
struct link_params *params, u32 action);
|
||||
struct bnx2x_reg_set {
|
||||
u8 devad;
|
||||
u16 reg;
|
||||
u16 val;
|
||||
};
|
||||
|
||||
struct bnx2x_phy {
|
||||
u32 type;
|
||||
|
|
|
|||
|
|
@ -7160,6 +7160,7 @@ Theotherbitsarereservedandshouldbezero*/
|
|||
#define MDIO_REG_GPHY_EEE_1G (0x1 << 2)
|
||||
#define MDIO_REG_GPHY_EEE_100 (0x1 << 1)
|
||||
#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
|
||||
#define MDIO_REG_GPHY_AUX_STATUS 0x19
|
||||
#define MDIO_REG_INTR_STATUS 0x1a
|
||||
#define MDIO_REG_INTR_MASK 0x1b
|
||||
#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue