drm/amdgpu: add RAS POISON interrupt funcs for jpeg_v4_0
Add ras_poison_irq and functions. And fix the amdgpu_irq_put call trace in jpeg_v4_0_hw_fini. [ 50.497562] RIP: 0010:amdgpu_irq_put+0xa4/0xc0 [amdgpu] [ 50.497619] RSP: 0018:ffffaa2400fcfcb0 EFLAGS: 00010246 [ 50.497620] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 [ 50.497621] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 [ 50.497621] RBP: ffffaa2400fcfcd0 R08: 0000000000000000 R09: 0000000000000000 [ 50.497622] R10: 0000000000000000 R11: 0000000000000000 R12: ffff99b2105242d8 [ 50.497622] R13: 0000000000000000 R14: ffff99b210500000 R15: ffff99b210500000 [ 50.497623] FS: 0000000000000000(0000) GS:ffff99b518480000(0000) knlGS:0000000000000000 [ 50.497623] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 50.497624] CR2: 00007f9d32aa91e8 CR3: 00000001ba210000 CR4: 0000000000750ee0 [ 50.497624] PKRU: 55555554 [ 50.497625] Call Trace: [ 50.497625] <TASK> [ 50.497627] jpeg_v4_0_hw_fini+0x43/0xc0 [amdgpu] [ 50.497693] jpeg_v4_0_suspend+0x13/0x30 [amdgpu] [ 50.497751] amdgpu_device_ip_suspend_phase2+0x240/0x470 [amdgpu] [ 50.497802] amdgpu_device_ip_suspend+0x41/0x80 [amdgpu] [ 50.497854] amdgpu_device_pre_asic_reset+0xd9/0x4a0 [amdgpu] [ 50.497905] amdgpu_device_gpu_recover.cold+0x548/0xcf1 [amdgpu] [ 50.498005] amdgpu_debugfs_reset_work+0x4c/0x80 [amdgpu] [ 50.498060] process_one_work+0x21f/0x400 [ 50.498063] worker_thread+0x200/0x3f0 [ 50.498064] ? process_one_work+0x400/0x400 [ 50.498065] kthread+0xee/0x120 [ 50.498067] ? kthread_complete_and_exit+0x20/0x20 [ 50.498068] ret_from_fork+0x22/0x30 Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Horatio Zhang <Hongkun.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -87,13 +87,13 @@ static int jpeg_v4_0_sw_init(void *handle)
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/* JPEG DJPEG POISON EVENT */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq);
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VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
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if (r)
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return r;
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/* JPEG EJPEG POISON EVENT */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq);
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VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
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if (r)
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return r;
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@ -202,7 +202,8 @@ static int jpeg_v4_0_hw_fini(void *handle)
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RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
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jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
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}
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amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0);
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
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amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
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return 0;
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}
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@ -670,6 +671,14 @@ static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev,
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return 0;
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}
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static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned int type,
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enum amdgpu_interrupt_state state)
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{
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return 0;
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}
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static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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@ -680,10 +689,6 @@ static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
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case VCN_4_0__SRCID__JPEG_DECODE:
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amdgpu_fence_process(adev->jpeg.inst->ring_dec);
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break;
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case VCN_4_0__SRCID_DJPEG0_POISON:
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case VCN_4_0__SRCID_EJPEG0_POISON:
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amdgpu_jpeg_process_poison_irq(adev, source, entry);
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break;
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default:
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DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
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entry->src_id, entry->src_data[0]);
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@ -753,10 +758,18 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {
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.process = jpeg_v4_0_process_interrupt,
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};
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static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = {
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.set = jpeg_v4_0_set_ras_interrupt_state,
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.process = amdgpu_jpeg_process_poison_irq,
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};
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static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->jpeg.inst->irq.num_types = 1;
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adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
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adev->jpeg.inst->ras_poison_irq.num_types = 1;
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adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
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}
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const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = {
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@ -811,6 +824,7 @@ const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = {
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static struct amdgpu_jpeg_ras jpeg_v4_0_ras = {
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.ras_block = {
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.hw_ops = &jpeg_v4_0_ras_hw_ops,
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.ras_late_init = amdgpu_jpeg_ras_late_init,
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},
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};
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