[PATCH] x86_64: Clean and enhance up K8 northbridge access code
- Factor out the duplicated access/cache code into a single file * Shared between i386/x86-64. - Share flush code between AGP and IOMMU * Fix a bug: AGP didn't wait for end of flush before - Drop 8 northbridges limit and allocate dynamically - Add lock to serialize AGP and IOMMU GART flushes - Add PCI ID for next AMD northbridge - Random related cleanups The old K8 NUMA discovery code is unchanged. New systems should all use SRAT for this. Cc: "Navin Boppuri" <navin.boppuri@newisys.com> Cc: Dave Jones <davej@redhat.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andi Kleen
Linus Torvalds
parent
7c2d9cd218
commit
a32073bffc
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@ -1054,6 +1054,10 @@ config SCx200
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This support is also available as a module. If compiled as a
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module, it will be called scx200.
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config K8_NB
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def_bool y
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depends on AGP_AMD64
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source "drivers/pcmcia/Kconfig"
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source "drivers/pci/hotplug/Kconfig"
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@ -37,6 +37,7 @@ obj-$(CONFIG_EFI) += efi.o efi_stub.o
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obj-$(CONFIG_DOUBLEFAULT) += doublefault.o
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obj-$(CONFIG_VM86) += vm86.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_K8_NB) += k8.o
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EXTRA_AFLAGS := -traditional
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@ -76,3 +77,6 @@ SYSCFLAGS_vsyscall-syms.o = -r
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$(obj)/vsyscall-syms.o: $(src)/vsyscall.lds \
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$(obj)/vsyscall-sysenter.o $(obj)/vsyscall-note.o FORCE
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$(call if_changed,syscall)
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k8-y += ../../x86_64/kernel/k8.o
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@ -501,6 +501,10 @@ config REORDER
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optimal TLB usage. If you have pretty much any version of binutils,
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this can increase your kernel build time by roughly one minute.
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config K8_NB
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def_bool y
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depends on AGP_AMD64 || GART_IOMMU || (PCI && NUMA)
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endmenu
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#
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@ -33,6 +33,7 @@ obj-$(CONFIG_SWIOTLB) += pci-swiotlb.o
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obj-$(CONFIG_KPROBES) += kprobes.o
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obj-$(CONFIG_X86_PM_TIMER) += pmtimer.o
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obj-$(CONFIG_X86_VSMP) += vsmp.o
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obj-$(CONFIG_K8_NB) += k8.o
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obj-$(CONFIG_MODULES) += module.o
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@ -24,6 +24,7 @@
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#include <asm/proto.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/k8.h>
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int iommu_aperture;
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int iommu_aperture_disabled __initdata = 0;
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@ -37,8 +38,6 @@ int fix_aperture __initdata = 1;
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/* This code runs before the PCI subsystem is initialized, so just
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access the northbridge directly. */
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#define NB_ID_3 (PCI_VENDOR_ID_AMD | (0x1103<<16))
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static u32 __init allocate_aperture(void)
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{
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pg_data_t *nd0 = NODE_DATA(0);
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@ -68,20 +67,20 @@ static u32 __init allocate_aperture(void)
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return (u32)__pa(p);
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}
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static int __init aperture_valid(char *name, u64 aper_base, u32 aper_size)
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static int __init aperture_valid(u64 aper_base, u32 aper_size)
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{
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if (!aper_base)
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return 0;
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if (aper_size < 64*1024*1024) {
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printk("Aperture from %s too small (%d MB)\n", name, aper_size>>20);
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printk("Aperture too small (%d MB)\n", aper_size>>20);
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return 0;
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}
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if (aper_base + aper_size >= 0xffffffff) {
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printk("Aperture from %s beyond 4GB. Ignoring.\n",name);
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printk("Aperture beyond 4GB. Ignoring.\n");
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return 0;
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}
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if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
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printk("Aperture from %s pointing to e820 RAM. Ignoring.\n",name);
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printk("Aperture pointing to e820 RAM. Ignoring.\n");
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return 0;
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}
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return 1;
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@ -140,7 +139,7 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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printk("Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
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aper, 32 << *order, apsizereg);
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if (!aperture_valid("AGP bridge", aper, (32*1024*1024) << *order))
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if (!aperture_valid(aper, (32*1024*1024) << *order))
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return 0;
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return (u32)aper;
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}
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@ -208,9 +207,8 @@ void __init iommu_hole_init(void)
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fix = 0;
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for (num = 24; num < 32; num++) {
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char name[30];
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if (read_pci_config(0, num, 3, 0x00) != NB_ID_3)
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continue;
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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iommu_aperture = 1;
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@ -222,9 +220,7 @@ void __init iommu_hole_init(void)
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printk("CPU %d: aperture @ %Lx size %u MB\n", num-24,
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aper_base, aper_size>>20);
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sprintf(name, "northbridge cpu %d", num-24);
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if (!aperture_valid(name, aper_base, aper_size)) {
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if (!aperture_valid(aper_base, aper_size)) {
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fix = 1;
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break;
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}
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@ -273,7 +269,7 @@ void __init iommu_hole_init(void)
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/* Fix up the north bridges */
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for (num = 24; num < 32; num++) {
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if (read_pci_config(0, num, 3, 0x00) != NB_ID_3)
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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/* Don't enable translation yet. That is done later.
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@ -0,0 +1,118 @@
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/*
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* Shared support code for AMD K8 northbridges and derivates.
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* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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*/
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#include <linux/gfp.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/k8.h>
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int num_k8_northbridges;
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EXPORT_SYMBOL(num_k8_northbridges);
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static u32 *flush_words;
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struct pci_device_id k8_nb_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
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{}
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};
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EXPORT_SYMBOL(k8_nb_ids);
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struct pci_dev **k8_northbridges;
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EXPORT_SYMBOL(k8_northbridges);
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static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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if (!dev)
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break;
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} while (!pci_match_id(&k8_nb_ids[0], dev));
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return dev;
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}
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int cache_k8_northbridges(void)
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{
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int i;
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struct pci_dev *dev;
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if (num_k8_northbridges)
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return 0;
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num_k8_northbridges = 0;
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dev = NULL;
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while ((dev = next_k8_northbridge(dev)) != NULL)
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num_k8_northbridges++;
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k8_northbridges = kmalloc((num_k8_northbridges + 1) * sizeof(void *),
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GFP_KERNEL);
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if (!k8_northbridges)
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return -ENOMEM;
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flush_words = kmalloc(num_k8_northbridges * sizeof(u32), GFP_KERNEL);
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if (!flush_words) {
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kfree(k8_northbridges);
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return -ENOMEM;
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}
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dev = NULL;
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i = 0;
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while ((dev = next_k8_northbridge(dev)) != NULL) {
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k8_northbridges[i++] = dev;
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pci_read_config_dword(dev, 0x9c, &flush_words[i]);
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}
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k8_northbridges[i] = NULL;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cache_k8_northbridges);
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/* Ignores subdevice/subvendor but as far as I can figure out
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they're useless anyways */
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int __init early_is_k8_nb(u32 device)
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{
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struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = k8_nb_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return 1;
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return 0;
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}
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void k8_flush_garts(void)
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{
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int flushed, i;
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unsigned long flags;
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static DEFINE_SPINLOCK(gart_lock);
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/* Avoid races between AGP and IOMMU. In theory it's not needed
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but I'm not sure if the hardware won't lose flush requests
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when another is pending. This whole thing is so expensive anyways
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that it doesn't matter to serialize more. -AK */
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spin_lock_irqsave(&gart_lock, flags);
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flushed = 0;
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for (i = 0; i < num_k8_northbridges; i++) {
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pci_write_config_dword(k8_northbridges[i], 0x9c,
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flush_words[i]|1);
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flushed++;
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}
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for (i = 0; i < num_k8_northbridges; i++) {
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u32 w;
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/* Make sure the hardware actually executed the flush*/
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for (;;) {
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pci_read_config_dword(k8_northbridges[i],
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0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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spin_unlock_irqrestore(&gart_lock, flags);
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if (!flushed)
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printk("nothing to flush?\n");
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}
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EXPORT_SYMBOL_GPL(k8_flush_garts);
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@ -32,6 +32,7 @@
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#include <asm/kdebug.h>
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#include <asm/swiotlb.h>
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#include <asm/dma.h>
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#include <asm/k8.h>
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unsigned long iommu_bus_base; /* GART remapping area (physical) */
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static unsigned long iommu_size; /* size of remapping area bytes */
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@ -46,8 +47,6 @@ u32 *iommu_gatt_base; /* Remapping table */
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also seen with Qlogic at least). */
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int iommu_fullflush = 1;
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#define MAX_NB 8
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/* Allocation bitmap for the remapping area */
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static DEFINE_SPINLOCK(iommu_bitmap_lock);
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static unsigned long *iommu_gart_bitmap; /* guarded by iommu_bitmap_lock */
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@ -63,13 +62,6 @@ static u32 gart_unmapped_entry;
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#define to_pages(addr,size) \
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(round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
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#define for_all_nb(dev) \
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dev = NULL; \
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while ((dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, dev))!=NULL)
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static struct pci_dev *northbridges[MAX_NB];
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static u32 northbridge_flush_word[MAX_NB];
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#define EMERGENCY_PAGES 32 /* = 128KB */
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#ifdef CONFIG_AGP
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@ -120,44 +112,17 @@ static void free_iommu(unsigned long offset, int size)
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/*
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* Use global flush state to avoid races with multiple flushers.
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*/
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static void flush_gart(struct device *dev)
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static void flush_gart(void)
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{
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unsigned long flags;
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int flushed = 0;
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int i, max;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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if (need_flush) {
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max = 0;
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for (i = 0; i < MAX_NB; i++) {
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if (!northbridges[i])
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continue;
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pci_write_config_dword(northbridges[i], 0x9c,
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northbridge_flush_word[i] | 1);
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flushed++;
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max = i;
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}
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for (i = 0; i <= max; i++) {
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u32 w;
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if (!northbridges[i])
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continue;
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/* Make sure the hardware actually executed the flush. */
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for (;;) {
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pci_read_config_dword(northbridges[i], 0x9c, &w);
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if (!(w & 1))
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break;
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cpu_relax();
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}
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}
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if (!flushed)
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printk("nothing to flush?\n");
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if (need_flush) {
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k8_flush_garts();
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need_flush = 0;
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}
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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}
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#ifdef CONFIG_IOMMU_LEAK
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#define SET_LEAK(x) if (iommu_leak_tab) \
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@ -266,7 +231,7 @@ static dma_addr_t gart_map_simple(struct device *dev, char *buf,
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size_t size, int dir)
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{
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dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
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flush_gart(dev);
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flush_gart();
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return map;
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}
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@ -351,7 +316,7 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
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s->dma_address = addr;
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s->dma_length = s->length;
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}
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flush_gart(dev);
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flush_gart();
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return nents;
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}
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@ -458,13 +423,13 @@ int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
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if (dma_map_cont(sg, start, i, sg+out, pages, need) < 0)
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goto error;
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out++;
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flush_gart(dev);
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flush_gart();
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if (out < nents)
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sg[out].dma_length = 0;
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return out;
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error:
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flush_gart(NULL);
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flush_gart();
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gart_unmap_sg(dev, sg, nents, dir);
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/* When it was forced or merged try again in a dumb way */
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if (force_iommu || iommu_merge) {
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@ -532,10 +497,13 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
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void *gatt;
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unsigned aper_base, new_aper_base;
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unsigned aper_size, gatt_size, new_aper_size;
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int i;
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printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
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aper_size = aper_base = info->aper_size = 0;
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for_all_nb(dev) {
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dev = NULL;
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for (i = 0; i < num_k8_northbridges; i++) {
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dev = k8_northbridges[i];
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new_aper_base = read_aperture(dev, &new_aper_size);
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if (!new_aper_base)
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goto nommu;
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@ -558,11 +526,12 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
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panic("Cannot allocate GATT table");
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memset(gatt, 0, gatt_size);
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agp_gatt_table = gatt;
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for_all_nb(dev) {
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for (i = 0; i < num_k8_northbridges; i++) {
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u32 ctl;
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u32 gatt_reg;
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dev = k8_northbridges[i];
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gatt_reg = __pa(gatt) >> 12;
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gatt_reg <<= 4;
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pci_write_config_dword(dev, 0x98, gatt_reg);
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@ -573,7 +542,7 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
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pci_write_config_dword(dev, 0x90, ctl);
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}
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flush_gart(NULL);
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flush_gart();
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printk("PCI-DMA: aperture base @ %x size %u KB\n",aper_base, aper_size>>10);
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return 0;
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@ -607,10 +576,14 @@ static int __init pci_iommu_init(void)
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struct agp_kern_info info;
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unsigned long aper_size;
|
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unsigned long iommu_start;
|
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struct pci_dev *dev;
|
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unsigned long scratch;
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long i;
|
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|
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if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
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printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
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return -1;
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}
|
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#ifndef CONFIG_AGP_AMD64
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no_agp = 1;
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#else
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|
|
@ -637,14 +610,6 @@ static int __init pci_iommu_init(void)
|
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return -1;
|
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}
|
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|
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i = 0;
|
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for_all_nb(dev)
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i++;
|
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if (i > MAX_NB) {
|
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printk(KERN_ERR "PCI-GART: Too many northbridges (%ld). Disabled\n", i);
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return -1;
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}
|
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|
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printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
|
||||
aper_size = info.aper_size * 1024 * 1024;
|
||||
iommu_size = check_iommu_size(info.aper_base, aper_size);
|
||||
|
|
@ -707,20 +672,8 @@ static int __init pci_iommu_init(void)
|
|||
for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
|
||||
iommu_gatt_base[i] = gart_unmapped_entry;
|
||||
|
||||
for_all_nb(dev) {
|
||||
u32 flag;
|
||||
int cpu = PCI_SLOT(dev->devfn) - 24;
|
||||
if (cpu >= MAX_NB)
|
||||
continue;
|
||||
northbridges[cpu] = dev;
|
||||
pci_read_config_dword(dev, 0x9c, &flag); /* cache flush word */
|
||||
northbridge_flush_word[cpu] = flag;
|
||||
}
|
||||
|
||||
flush_gart(NULL);
|
||||
|
||||
flush_gart();
|
||||
dma_ops = &gart_dma_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
#include <linux/pci.h>
|
||||
#include <asm/mpspec.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <asm/k8.h>
|
||||
|
||||
/*
|
||||
* This discovers the pcibus <-> node mapping on AMD K8.
|
||||
|
|
@ -18,7 +19,6 @@
|
|||
#define NR_LDT_BUS_NUMBER_REGISTERS 3
|
||||
#define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 8) & 0xFF)
|
||||
#define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF)
|
||||
#define PCI_DEVICE_ID_K8HTCONFIG 0x1100
|
||||
|
||||
/**
|
||||
* fill_mp_bus_to_cpumask()
|
||||
|
|
@ -28,8 +28,7 @@
|
|||
__init static int
|
||||
fill_mp_bus_to_cpumask(void)
|
||||
{
|
||||
struct pci_dev *nb_dev = NULL;
|
||||
int i, j;
|
||||
int i, j, k;
|
||||
u32 ldtbus, nid;
|
||||
static int lbnr[3] = {
|
||||
LDT_BUS_NUMBER_REGISTER_0,
|
||||
|
|
@ -37,8 +36,9 @@ fill_mp_bus_to_cpumask(void)
|
|||
LDT_BUS_NUMBER_REGISTER_2
|
||||
};
|
||||
|
||||
while ((nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_K8HTCONFIG, nb_dev))) {
|
||||
cache_k8_northbridges();
|
||||
for (k = 0; k < num_k8_northbridges; k++) {
|
||||
struct pci_dev *nb_dev = k8_northbridges[k];
|
||||
pci_read_config_dword(nb_dev, NODE_ID_REGISTER, &nid);
|
||||
|
||||
for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) {
|
||||
|
|
|
|||
|
|
@ -15,11 +15,9 @@
|
|||
#include <linux/agp_backend.h>
|
||||
#include <linux/mmzone.h>
|
||||
#include <asm/page.h> /* PAGE_SIZE */
|
||||
#include <asm/k8.h>
|
||||
#include "agp.h"
|
||||
|
||||
/* Will need to be increased if AMD64 ever goes >8-way. */
|
||||
#define MAX_HAMMER_GARTS 8
|
||||
|
||||
/* PTE bits. */
|
||||
#define GPTE_VALID 1
|
||||
#define GPTE_COHERENT 2
|
||||
|
|
@ -53,28 +51,12 @@
|
|||
#define ULI_X86_64_HTT_FEA_REG 0x50
|
||||
#define ULI_X86_64_ENU_SCR_REG 0x54
|
||||
|
||||
static int nr_garts;
|
||||
static struct pci_dev * hammers[MAX_HAMMER_GARTS];
|
||||
|
||||
static struct resource *aperture_resource;
|
||||
static int __initdata agp_try_unsupported = 1;
|
||||
|
||||
#define for_each_nb() for(gart_iterator=0;gart_iterator<nr_garts;gart_iterator++)
|
||||
|
||||
static void flush_amd64_tlb(struct pci_dev *dev)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp);
|
||||
tmp |= INVGART;
|
||||
pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp);
|
||||
}
|
||||
|
||||
static void amd64_tlbflush(struct agp_memory *temp)
|
||||
{
|
||||
int gart_iterator;
|
||||
for_each_nb()
|
||||
flush_amd64_tlb(hammers[gart_iterator]);
|
||||
k8_flush_garts();
|
||||
}
|
||||
|
||||
static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
|
||||
|
|
@ -153,7 +135,7 @@ static int amd64_fetch_size(void)
|
|||
u32 temp;
|
||||
struct aper_size_info_32 *values;
|
||||
|
||||
dev = hammers[0];
|
||||
dev = k8_northbridges[0];
|
||||
if (dev==NULL)
|
||||
return 0;
|
||||
|
||||
|
|
@ -201,9 +183,6 @@ static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
|
|||
tmp &= ~(DISGARTCPU | DISGARTIO);
|
||||
pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
|
||||
|
||||
/* keep CPU's coherent. */
|
||||
flush_amd64_tlb (hammer);
|
||||
|
||||
return aper_base;
|
||||
}
|
||||
|
||||
|
|
@ -222,13 +201,14 @@ static struct aper_size_info_32 amd_8151_sizes[7] =
|
|||
static int amd_8151_configure(void)
|
||||
{
|
||||
unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
|
||||
int gart_iterator;
|
||||
int i;
|
||||
|
||||
/* Configure AGP regs in each x86-64 host bridge. */
|
||||
for_each_nb() {
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
agp_bridge->gart_bus_addr =
|
||||
amd64_configure(hammers[gart_iterator],gatt_bus);
|
||||
amd64_configure(k8_northbridges[i], gatt_bus);
|
||||
}
|
||||
k8_flush_garts();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -236,12 +216,13 @@ static int amd_8151_configure(void)
|
|||
static void amd64_cleanup(void)
|
||||
{
|
||||
u32 tmp;
|
||||
int gart_iterator;
|
||||
for_each_nb() {
|
||||
int i;
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
struct pci_dev *dev = k8_northbridges[i];
|
||||
/* disable gart translation */
|
||||
pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp);
|
||||
pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
|
||||
tmp &= ~AMD64_GARTEN;
|
||||
pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp);
|
||||
pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -361,17 +342,15 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
|
|||
|
||||
static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
|
||||
{
|
||||
struct pci_dev *loop_dev = NULL;
|
||||
int i = 0;
|
||||
int i;
|
||||
|
||||
/* cache pci_devs of northbridges. */
|
||||
while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev))
|
||||
!= NULL) {
|
||||
if (i == MAX_HAMMER_GARTS) {
|
||||
printk(KERN_ERR PFX "Too many northbridges for AGP\n");
|
||||
return -1;
|
||||
}
|
||||
if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) {
|
||||
if (cache_k8_northbridges() < 0)
|
||||
return -ENODEV;
|
||||
|
||||
i = 0;
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
struct pci_dev *dev = k8_northbridges[i];
|
||||
if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
|
||||
printk(KERN_ERR PFX "No usable aperture found.\n");
|
||||
#ifdef __x86_64__
|
||||
/* should port this to i386 */
|
||||
|
|
@ -379,10 +358,8 @@ static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
|
|||
#endif
|
||||
return -1;
|
||||
}
|
||||
hammers[i++] = loop_dev;
|
||||
}
|
||||
nr_garts = i;
|
||||
return i == 0 ? -1 : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Handle AMD 8151 quirks */
|
||||
|
|
@ -450,7 +427,7 @@ static int __devinit uli_agp_init(struct pci_dev *pdev)
|
|||
}
|
||||
|
||||
/* shadow x86-64 registers into ULi registers */
|
||||
pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea);
|
||||
pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
|
||||
|
||||
/* if x86-64 aperture base is beyond 4G, exit here */
|
||||
if ((httfea & 0x7fff) >> (32 - 25))
|
||||
|
|
@ -513,7 +490,7 @@ static int __devinit nforce3_agp_init(struct pci_dev *pdev)
|
|||
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
|
||||
|
||||
/* shadow x86-64 registers into NVIDIA registers */
|
||||
pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase);
|
||||
pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
|
||||
|
||||
/* if x86-64 aperture base is beyond 4G, exit here */
|
||||
if ( (apbase & 0x7fff) >> (32 - 25) ) {
|
||||
|
|
@ -754,10 +731,6 @@ static struct pci_driver agp_amd64_pci_driver = {
|
|||
int __init agp_amd64_init(void)
|
||||
{
|
||||
int err = 0;
|
||||
static struct pci_device_id amd64nb[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
|
||||
{ },
|
||||
};
|
||||
|
||||
if (agp_off)
|
||||
return -EINVAL;
|
||||
|
|
@ -774,7 +747,7 @@ int __init agp_amd64_init(void)
|
|||
}
|
||||
|
||||
/* First check that we have at least one AMD64 NB */
|
||||
if (!pci_dev_present(amd64nb))
|
||||
if (!pci_dev_present(k8_nb_ids))
|
||||
return -ENODEV;
|
||||
|
||||
/* Look for any AGP bridge */
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
#include <asm-x86_64/k8.h>
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef _ASM_K8_H
|
||||
#define _ASM_K8_H 1
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
extern struct pci_device_id k8_nb_ids[];
|
||||
|
||||
extern int early_is_k8_nb(u32 value);
|
||||
extern struct pci_dev **k8_northbridges;
|
||||
extern int num_k8_northbridges;
|
||||
extern int cache_k8_northbridges(void);
|
||||
extern void k8_flush_garts(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue