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drm/amdgpu/sdma4: use common function to init sdma fw 

Use common function to init sdma v4 firmware ucode.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2022-09-22 14:37:52 +08:00 committed by Alex Deucher
parent 15aa13056d
commit a2d3b4b81f
1 changed files with 19 additions and 88 deletions
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107
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
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@ -561,44 +561,6 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
} }
} }
static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
{
int err = 0;
const struct sdma_firmware_header_v1_0 *hdr;
err = amdgpu_ucode_validate(sdma_inst->fw);
if (err)
return err;
hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
if (sdma_inst->feature_version >= 20)
sdma_inst->burst_nop = true;
return 0;
}
static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
release_firmware(adev->sdma.instance[i].fw);
adev->sdma.instance[i].fw = NULL;
/* arcturus shares the same FW memory across
all SDMA isntances */
if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
break;
}
memset((void *)adev->sdma.instance, 0,
sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
}
/** /**
* sdma_v4_0_init_microcode - load ucode images from disk * sdma_v4_0_init_microcode - load ucode images from disk
* *
@ -615,9 +577,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
{ {
const char *chip_name; const char *chip_name;
char fw_name[30]; char fw_name[30];
int err = 0, i; int ret, i;
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
@ -656,58 +616,25 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
BUG(); BUG();
} }
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); for (i = 0; i < adev->sdma.num_instances; i++) {
if (i == 0)
err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
if (err) else
goto out; snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) ||
err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
if (err)
goto out;
for (i = 1; i < adev->sdma.num_instances; i++) {
if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
/* Acturus & Aldebaran will leverage the same FW memory /* Acturus & Aldebaran will leverage the same FW memory
for every SDMA instance */ for every SDMA instance */
memcpy((void *)&adev->sdma.instance[i], ret = amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
(void *)&adev->sdma.instance[0], break;
sizeof(struct amdgpu_sdma_instance)); } else {
} ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false);
else { if (ret)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); return ret;
err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
if (err)
goto out;
err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
if (err)
goto out;
} }
} }
DRM_DEBUG("psp_load == '%s'\n", return ret;
adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
for (i = 0; i < adev->sdma.num_instances; i++) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
info->fw = adev->sdma.instance[i].fw;
header = (const struct common_firmware_header *)info->fw->data;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
}
}
out:
if (err) {
DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
sdma_v4_0_destroy_inst_ctx(adev);
}
return err;
} }
/** /**
@ -2000,7 +1927,11 @@ static int sdma_v4_0_sw_fini(void *handle)
amdgpu_ring_fini(&adev->sdma.instance[i].page); amdgpu_ring_fini(&adev->sdma.instance[i].page);
} }
sdma_v4_0_destroy_inst_ctx(adev); if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0) ||
adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
amdgpu_sdma_destroy_inst_ctx(adev, true);
else
amdgpu_sdma_destroy_inst_ctx(adev, false);
return 0; return 0;
} }