arm64: tegra: Device tree changes for v4.15-rc1
Enables host1x, VIC, PCIe and the BPMP thermal sensor on Tegra186. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlnp4kkTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoRzED/0UbIFfK3R8EreqoPDdxqBZN471PcMo zAiYoSZ3WOHhbsexhpgJRUiHUpW4C0RnguG6x1QXN5Gt0EuIy4ydeYjLX6r1jcZi 74ZxGgHvOipCj83CspGV0oGcys4c3A/KpSLBH/+7oy9YUXQ/xo2g9kj0941wP22a 4kCiVOSjEXOP7m25GJ4MistFqkIOdkEEWBUGghsCxYFoZEGngKgG0PKEhb4ta/BQ i8i6h9NmzF1LyAA2Vka3mn3XmvF+EM58L4eUt3deNlMqW/mIc5wcXJwzXKFbyTxp c7V2V0EcU2sANg6/MjAf33VQLg5TkM04REJE7MBZ+FrTLxSn1hA4unLoeWN5Q6Hf pRmjvQhH49Dl3rX2cNMGGAHfK4oRsWjfX5dlNBA1ub0HlBlClNRRf87A4rkg12tx RIdFGF9B8sjddAUItXdPLzfNqaLkfk9fePS2bRfqChMlPYvPynQrUe3sVKhkjPDm O8NevnC+eYYeNWNKRp4RM19RW5/McZup03LQLN62BehQlUxb3Tpe3EIJOdbHdMYb 5m5cSj9YERk8boS1LOUG3orN/LAAR/G1uU2T12w7+PN8xagN+Uic6JMMF34/87j+ LdYGEaWV/6tr8J1ull6wFTlsNPmuGJ8IxS5y6o5qn9oZOXK2UVoymluC5kFkx+hB oEcNdBIxSM679Q== =AvTC -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.15-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Pull "arm64: tegra: Device tree changes for v4.15-rc1" from Thierry Reding: Enables host1x, VIC, PCIe and the BPMP thermal sensor on Tegra186. * tag 'tegra-for-4.15-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add BPMP thermal sensor to Tegra186 arm64: tegra: Enable PCIe on Jetson TX2 arm64: tegra: Add PCIe node for Tegra186 arm64: tegra: Add VIC on Tegra186 arm64: tegra: Add host1x on Tegra186 arm64: tegra: Add #power-domain-cells for BPMP
This commit is contained in:
Arnd Bergmann
commit
a2c614a7db
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@ -49,6 +49,30 @@
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vmmc-supply = <&vdd_sd>;
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};
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pcie@10003000 {
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status = "okay";
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dvdd-pex-supply = <&vdd_pex>;
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hvdd-pex-pll-supply = <&vdd_1v8>;
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hvdd-pex-supply = <&vdd_1v8>;
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vddio-pexctl-aud-supply = <&vdd_1v8>;
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pci@1,0 {
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nvidia,num-lanes = <4>;
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status = "okay";
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};
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pci@2,0 {
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nvidia,num-lanes = <0>;
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status = "disabled";
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};
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pci@3,0 {
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nvidia,num-lanes = <1>;
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status = "disabled";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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@ -4,6 +4,7 @@
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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/ {
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compatible = "nvidia,tegra186";
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@ -355,6 +356,116 @@
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nvidia,bpmp = <&bpmp>;
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};
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pcie@10003000 {
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compatible = "nvidia,tegra186-pcie";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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0x0 0x10003800 0x0 0x00000800 /* AFI registers */
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0x0 0x40000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
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0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
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clocks = <&bpmp TEGRA186_CLK_AFI>,
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<&bpmp TEGRA186_CLK_PCIE>,
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<&bpmp TEGRA186_CLK_PLLE>;
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clock-names = "afi", "pex", "pll_e";
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resets = <&bpmp TEGRA186_RESET_AFI>,
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<&bpmp TEGRA186_RESET_PCIE>,
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<&bpmp TEGRA186_RESET_PCIEXCLK>;
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reset-names = "afi", "pex", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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host1x@13e00000 {
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compatible = "nvidia,tegra186-host1x", "simple-bus";
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reg = <0x0 0x13e00000 0x0 0x10000>,
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<0x0 0x13e10000 0x0 0x10000>;
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reg-names = "hypervisor", "vm";
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_HOST1X>;
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clock-names = "host1x";
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resets = <&bpmp TEGRA186_RESET_HOST1X>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x15000000 0x0 0x15000000 0x01000000>;
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vic@15340000 {
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compatible = "nvidia,tegra186-vic";
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reg = <0x15340000 0x40000>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_VIC>;
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clock-names = "vic";
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resets = <&bpmp TEGRA186_RESET_VIC>;
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reset-names = "vic";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
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};
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};
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gpu@17000000 {
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compatible = "nvidia,gp10b";
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reg = <0x0 0x17000000 0x0 0x1000000>,
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@ -443,6 +554,7 @@
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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bpmp_i2c: i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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@ -451,6 +563,108 @@
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#size-cells = <0>;
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status = "disabled";
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};
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bpmp_thermal: thermal {
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compatible = "nvidia,tegra186-bpmp-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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thermal-zones {
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a57 {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors =
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<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
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trips {
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critical {
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temperature = <101000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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denver {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors =
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<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
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trips {
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critical {
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temperature = <101000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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gpu {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors =
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<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
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trips {
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critical {
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temperature = <101000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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pll {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors =
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<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
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trips {
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critical {
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temperature = <101000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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always_on {
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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thermal-sensors =
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<&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
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trips {
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critical {
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temperature = <101000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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};
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timer {
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