drm/amd/display: dc: Remove unused display_mode_vba.c
We're currently not using this. v2: More files and includes to remove. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland
Alex Deucher
parent
f75a9a5d6c
commit
a27267e01f
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@ -27,16 +27,14 @@
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CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
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CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
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DML = display_mode_lib.o display_rq_dlg_calc.o \
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display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
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soc_bounding_box.o dml_common_defs.o display_mode_vba.o
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DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
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soc_bounding_box.o dml_common_defs.o
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AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
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@ -28,8 +28,6 @@
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#include "dml_common_defs.h"
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#include "soc_bounding_box.h"
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#include "display_mode_vba.h"
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#include "display_rq_dlg_calc.h"
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#include "dml1_display_rq_dlg_calc.h"
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enum dml_project {
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@ -41,7 +39,6 @@ struct display_mode_lib {
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struct _vcs_dpi_ip_params_st ip;
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struct _vcs_dpi_soc_bounding_box_st soc;
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enum dml_project project;
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struct vba_vars_st vba;
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struct dal_logger *logger;
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};
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File diff suppressed because it is too large
Load Diff
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@ -1,598 +0,0 @@
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DML2_DISPLAY_MODE_VBA_H__
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#define __DML2_DISPLAY_MODE_VBA_H__
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#include "dml_common_defs.h"
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struct display_mode_lib;
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void set_prefetch_mode(struct display_mode_lib *mode_lib,
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bool cstate_en,
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bool pstate_en,
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bool ignore_viewport_pos,
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bool immediate_flip_support);
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#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
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dml_get_attr_decl(clk_dcf_deepsleep);
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dml_get_attr_decl(wm_urgent);
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dml_get_attr_decl(wm_memory_trip);
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dml_get_attr_decl(wm_writeback_urgent);
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dml_get_attr_decl(wm_stutter_exit);
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dml_get_attr_decl(wm_stutter_enter_exit);
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dml_get_attr_decl(wm_dram_clock_change);
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dml_get_attr_decl(wm_writeback_dram_clock_change);
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dml_get_attr_decl(wm_xfc_underflow);
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dml_get_attr_decl(stutter_efficiency_no_vblank);
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dml_get_attr_decl(stutter_efficiency);
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dml_get_attr_decl(urgent_latency);
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dml_get_attr_decl(urgent_extra_latency);
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dml_get_attr_decl(nonurgent_latency);
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dml_get_attr_decl(dram_clock_change_latency);
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dml_get_attr_decl(dispclk_calculated);
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dml_get_attr_decl(total_data_read_bw);
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dml_get_attr_decl(return_bw);
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dml_get_attr_decl(tcalc);
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#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
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dml_get_pipe_attr_decl(dsc_delay);
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dml_get_pipe_attr_decl(dppclk_calculated);
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dml_get_pipe_attr_decl(dscclk_calculated);
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dml_get_pipe_attr_decl(min_ttu_vblank);
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dml_get_pipe_attr_decl(vratio_prefetch_l);
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dml_get_pipe_attr_decl(vratio_prefetch_c);
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dml_get_pipe_attr_decl(dst_x_after_scaler);
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dml_get_pipe_attr_decl(dst_y_after_scaler);
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dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
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dml_get_pipe_attr_decl(dst_y_per_row_vblank);
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dml_get_pipe_attr_decl(dst_y_prefetch);
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dml_get_pipe_attr_decl(dst_y_per_vm_flip);
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dml_get_pipe_attr_decl(dst_y_per_row_flip);
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dml_get_pipe_attr_decl(xfc_transfer_delay);
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dml_get_pipe_attr_decl(xfc_precharge_delay);
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dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
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dml_get_pipe_attr_decl(xfc_prefetch_margin);
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unsigned int get_vstartup_calculated(
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *pipes,
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unsigned int num_pipes,
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unsigned int which_pipe);
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double get_total_immediate_flip_bytes(
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *pipes,
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unsigned int num_pipes);
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double get_total_immediate_flip_bw(
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *pipes,
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unsigned int num_pipes);
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double get_total_prefetch_bw(
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *pipes,
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unsigned int num_pipes);
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unsigned int dml_get_voltage_level(
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *pipes,
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unsigned int num_pipes);
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bool Calculate256BBlockSizes(
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enum source_format_class SourcePixelFormat,
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enum dm_swizzle_mode SurfaceTiling,
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unsigned int BytePerPixelY,
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unsigned int BytePerPixelC,
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unsigned int *BlockHeight256BytesY,
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unsigned int *BlockHeight256BytesC,
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unsigned int *BlockWidth256BytesY,
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unsigned int *BlockWidth256BytesC);
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struct vba_vars_st {
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ip_params_st ip;
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soc_bounding_box_st soc;
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unsigned int MaximumMaxVStartupLines;
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double cursor_bw[DC__NUM_DPP__MAX];
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double meta_row_bw[DC__NUM_DPP__MAX];
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double dpte_row_bw[DC__NUM_DPP__MAX];
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double qual_row_bw[DC__NUM_DPP__MAX];
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double WritebackDISPCLK;
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double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
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double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
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double DPPCLKUsingSingleDPPLuma;
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double DPPCLKUsingSingleDPPChroma;
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double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
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double DISPCLKWithRamping;
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double DISPCLKWithoutRamping;
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double GlobalDPPCLK;
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double DISPCLKWithRampingRoundedToDFSGranularity;
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double DISPCLKWithoutRampingRoundedToDFSGranularity;
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double MaxDispclkRoundedToDFSGranularity;
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bool DCCEnabledAnyPlane;
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double ReturnBandwidthToDCN;
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unsigned int SwathWidthY[DC__NUM_DPP__MAX];
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unsigned int SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
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double BytePerPixelDETY[DC__NUM_DPP__MAX];
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double BytePerPixelDETC[DC__NUM_DPP__MAX];
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double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
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double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
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unsigned int TotalActiveDPP;
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unsigned int TotalDCCActiveDPP;
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double UrgentRoundTripAndOutOfOrderLatency;
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double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
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double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
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double LinesInDETY[DC__NUM_DPP__MAX]; // WM
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double LinesInDETC[DC__NUM_DPP__MAX]; // WM
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unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; // WM
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unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; // WM
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double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
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double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
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double MinFullDETBufferingTime;
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double FrameTimeForMinFullDETBufferingTime;
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double AverageReadBandwidthGBytePerSecond;
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double PartOfBurstThatFitsInROB;
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double StutterBurstTime;
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//unsigned int NextPrefetchMode;
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double VBlankTime;
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double SmallestVBlank;
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double DCFCLKDeepSleepPerPlane;
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double EffectiveDETPlusLBLinesLuma;
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double EffectiveDETPlusLBLinesChroma;
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double UrgentLatencySupportUsLuma;
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double UrgentLatencySupportUsChroma;
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double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
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unsigned int DSCFormatFactor;
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unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
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unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
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unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
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unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
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double VInitPreFillY[DC__NUM_DPP__MAX];
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double VInitPreFillC[DC__NUM_DPP__MAX];
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unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
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unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
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double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
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double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
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double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
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double MetaRowByte[DC__NUM_DPP__MAX];
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unsigned int dpte_row_height[DC__NUM_DPP__MAX];
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unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
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unsigned int meta_row_height[DC__NUM_DPP__MAX];
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unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
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unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
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unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
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unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
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double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
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bool PrefetchModeSupported;
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bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
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bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
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double RequiredPrefetchPixDataBW[DC__NUM_DPP__MAX];
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double XFCRemoteSurfaceFlipDelay;
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double TInitXFill;
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double TslvChk;
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double SrcActiveDrainRate;
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double Tno_bw[DC__NUM_DPP__MAX];
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bool ImmediateFlipSupported;
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double prefetch_vm_bw[DC__NUM_DPP__MAX];
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double prefetch_row_bw[DC__NUM_DPP__MAX];
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bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
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unsigned int VStartupLines;
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double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
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double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
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unsigned int ActiveDPPs;
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unsigned int LBLatencyHidingSourceLinesY;
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unsigned int LBLatencyHidingSourceLinesC;
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double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
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double MinActiveDRAMClockChangeMargin;
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double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
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double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
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double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
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double InitFillLevel;
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double FinalFillMargin;
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double FinalFillLevel;
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double RemainingFillLevel;
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double TFinalxFill;
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//
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// SOC Bounding Box Parameters
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//
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double SRExitTime;
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double SREnterPlusExitTime;
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double UrgentLatency;
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double WritebackLatency;
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double PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency;
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double NumberOfChannels;
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double DRAMChannelWidth;
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double FabricDatapathToDCNDataReturn;
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double ReturnBusWidth;
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double Downspreading;
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double DISPCLKDPPCLKDSCCLKDownSpreading;
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double DISPCLKDPPCLKVCOSpeed;
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double RoundTripPingLatencyCycles;
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double UrgentOutOfOrderReturnPerChannel;
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unsigned int VMMPageSize;
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double DRAMClockChangeLatency;
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double XFCBusTransportTime;
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double XFCXBUFLatencyTolerance;
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//
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// IP Parameters
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//
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unsigned int ROBBufferSizeInKByte;
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double DETBufferSizeInKByte;
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unsigned int DPPOutputBufferPixels;
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unsigned int OPPOutputBufferLines;
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unsigned int PixelChunkSizeInKByte;
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double ReturnBW;
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bool VirtualMemoryEnable;
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unsigned int MaxPageTableLevels;
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unsigned int OverridePageTableLevels;
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unsigned int PTEChunkSize;
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unsigned int MetaChunkSize;
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unsigned int WritebackChunkSize;
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bool ODMCapability;
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unsigned int NumberOfDSC;
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unsigned int LineBufferSize;
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unsigned int MaxLineBufferLines;
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unsigned int WritebackInterfaceLumaBufferSize;
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unsigned int WritebackInterfaceChromaBufferSize;
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unsigned int WritebackChromaLineBufferWidth;
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double MaxDCHUBToPSCLThroughput;
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double MaxPSCLToLBThroughput;
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unsigned int PTEBufferSizeInRequests;
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double DISPCLKRampingMargin;
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unsigned int MaxInterDCNTileRepeaters;
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bool XFCSupported;
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double XFCSlvChunkSize;
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double XFCFillBWOverhead;
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double XFCFillConstant;
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double XFCTSlvVupdateOffset;
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double XFCTSlvVupdateWidth;
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double XFCTSlvVreadyOffset;
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double DPPCLKDelaySubtotal;
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double DPPCLKDelaySCL;
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double DPPCLKDelaySCLLBOnly;
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double DPPCLKDelayCNVCFormater;
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double DPPCLKDelayCNVCCursor;
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double DISPCLKDelaySubtotal;
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bool ProgressiveToInterlaceUnitInOPP;
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unsigned int PDEProcessingBufIn64KBReqs;
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// Pipe/Plane Parameters
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int VoltageLevel;
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double FabricAndDRAMBandwidth;
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double FabricClock;
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double DRAMSpeed;
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double DISPCLK;
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double SOCCLK;
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double DCFCLK;
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unsigned int NumberOfActivePlanes;
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unsigned int ViewportWidth[DC__NUM_DPP__MAX];
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unsigned int ViewportHeight[DC__NUM_DPP__MAX];
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unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
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unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
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unsigned int PitchY[DC__NUM_DPP__MAX];
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unsigned int PitchC[DC__NUM_DPP__MAX];
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double HRatio[DC__NUM_DPP__MAX];
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double VRatio[DC__NUM_DPP__MAX];
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unsigned int htaps[DC__NUM_DPP__MAX];
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unsigned int vtaps[DC__NUM_DPP__MAX];
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unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
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unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
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unsigned int HTotal[DC__NUM_DPP__MAX];
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unsigned int VTotal[DC__NUM_DPP__MAX];
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unsigned int DPPPerPlane[DC__NUM_DPP__MAX];
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double PixelClock[DC__NUM_DPP__MAX];
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double PixelClockBackEnd[DC__NUM_DPP__MAX];
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double DPPCLK[DC__NUM_DPP__MAX];
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bool DCCEnable[DC__NUM_DPP__MAX];
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unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
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enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
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enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
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bool WritebackEnable[DC__NUM_DPP__MAX];
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double WritebackDestinationWidth[DC__NUM_DPP__MAX];
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double WritebackDestinationHeight[DC__NUM_DPP__MAX];
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double WritebackSourceHeight[DC__NUM_DPP__MAX];
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enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
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unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
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unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
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unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
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unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
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double WritebackHRatio[DC__NUM_DPP__MAX];
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double WritebackVRatio[DC__NUM_DPP__MAX];
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unsigned int HActive[DC__NUM_DPP__MAX];
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unsigned int VActive[DC__NUM_DPP__MAX];
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bool Interlace[DC__NUM_DPP__MAX];
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enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
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unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
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bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
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unsigned int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
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unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
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double DCCRate[DC__NUM_DPP__MAX];
|
||||
bool ODMCombineEnabled[DC__NUM_DPP__MAX];
|
||||
double OutputBpp[DC__NUM_DPP__MAX];
|
||||
unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
|
||||
bool DSCEnabled[DC__NUM_DPP__MAX];
|
||||
unsigned int DSCDelay[DC__NUM_DPP__MAX];
|
||||
unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
|
||||
enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
|
||||
enum output_encoder_class Output[DC__NUM_DPP__MAX];
|
||||
unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
|
||||
bool SynchronizedVBlank;
|
||||
unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
|
||||
unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
|
||||
unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
|
||||
bool XFCEnabled[DC__NUM_DPP__MAX];
|
||||
bool ScalerEnabled[DC__NUM_DPP__MAX];
|
||||
|
||||
// Intermediates/Informational
|
||||
bool ImmediateFlipSupport;
|
||||
unsigned int SwathHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int SwathHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
|
||||
unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
|
||||
unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
|
||||
double LastPixelOfLineExtraWatermark;
|
||||
double TotalDataReadBandwidth;
|
||||
unsigned int TotalActiveWriteback;
|
||||
unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
|
||||
unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
|
||||
double BandwidthAvailableForImmediateFlip;
|
||||
unsigned int PrefetchMode;
|
||||
bool IgnoreViewportPositioning;
|
||||
double PrefetchBandwidth[DC__NUM_DPP__MAX];
|
||||
bool ErrorResult[DC__NUM_DPP__MAX];
|
||||
double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
|
||||
|
||||
//
|
||||
// Calculated dml_ml->vba.Outputs
|
||||
//
|
||||
double DCFClkDeepSleep;
|
||||
double UrgentWatermark;
|
||||
double UrgentExtraLatency;
|
||||
double MemoryTripWatermark;
|
||||
double WritebackUrgentWatermark;
|
||||
double StutterExitWatermark;
|
||||
double StutterEnterPlusExitWatermark;
|
||||
double DRAMClockChangeWatermark;
|
||||
double WritebackDRAMClockChangeWatermark;
|
||||
double StutterEfficiency;
|
||||
double StutterEfficiencyNotIncludingVBlank;
|
||||
double MinUrgentLatencySupportUs;
|
||||
double NonUrgentLatencyTolerance;
|
||||
double MinActiveDRAMClockChangeLatencySupported;
|
||||
enum clock_change_support DRAMClockChangeSupport;
|
||||
|
||||
// These are the clocks calcuated by the library but they are not actually
|
||||
// used explicitly. They are fetched by tests and then possibly used. The
|
||||
// ultimate values to use are the ones specified by the parameters to DML
|
||||
double DISPCLK_calculated;
|
||||
double DSCCLK_calculated[DC__NUM_DPP__MAX];
|
||||
double DPPCLK_calculated[DC__NUM_DPP__MAX];
|
||||
|
||||
unsigned int VStartup[DC__NUM_DPP__MAX];
|
||||
unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
|
||||
unsigned int VUpdateWidthPix[DC__NUM_DPP__MAX];
|
||||
unsigned int VReadyOffsetPix[DC__NUM_DPP__MAX];
|
||||
unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
|
||||
|
||||
double ImmediateFlipBW;
|
||||
unsigned int TotImmediateFlipBytes;
|
||||
double TCalc;
|
||||
double MinTTUVBlank[DC__NUM_DPP__MAX];
|
||||
double VRatioPrefetchY[DC__NUM_DPP__MAX];
|
||||
double VRatioPrefetchC[DC__NUM_DPP__MAX];
|
||||
double DSTXAfterScaler[DC__NUM_DPP__MAX];
|
||||
double DSTYAfterScaler[DC__NUM_DPP__MAX];
|
||||
|
||||
double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
|
||||
double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
|
||||
double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
|
||||
double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
|
||||
double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
|
||||
|
||||
double XFCTransferDelay[DC__NUM_DPP__MAX];
|
||||
double XFCPrechargeDelay[DC__NUM_DPP__MAX];
|
||||
double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
|
||||
double XFCPrefetchMargin[DC__NUM_DPP__MAX];
|
||||
|
||||
display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
|
||||
unsigned int cache_num_pipes;
|
||||
unsigned int pipe_plane[DC__NUM_DPP__MAX];
|
||||
|
||||
/* vba mode support */
|
||||
/*inputs*/
|
||||
bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
|
||||
double MaxHSCLRatio;
|
||||
double MaxVSCLRatio;
|
||||
unsigned int MaxNumWriteback;
|
||||
bool WritebackLumaAndChromaScalingSupported;
|
||||
bool Cursor64BppSupport;
|
||||
double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
|
||||
double FabricClockPerState[DC__VOLTAGE_STATES + 1];
|
||||
double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
|
||||
double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
|
||||
double MaxDppclk[DC__VOLTAGE_STATES + 1];
|
||||
double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
|
||||
double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
|
||||
double MaxDispclk[DC__VOLTAGE_STATES + 1];
|
||||
|
||||
/*outputs*/
|
||||
bool ScaleRatioAndTapsSupport;
|
||||
bool SourceFormatPixelAndScanSupport;
|
||||
unsigned int SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
|
||||
double BytePerPixelInDETY[DC__NUM_DPP__MAX];
|
||||
double BytePerPixelInDETC[DC__NUM_DPP__MAX];
|
||||
double TotalReadBandwidthConsumedGBytePerSecond;
|
||||
double ReadBandwidth[DC__NUM_DPP__MAX];
|
||||
double TotalWriteBandwidthConsumedGBytePerSecond;
|
||||
double WriteBandwidth[DC__NUM_DPP__MAX];
|
||||
double TotalBandwidthConsumedGBytePerSecond;
|
||||
bool DCCEnabledInAnyPlane;
|
||||
bool WritebackLatencySupport;
|
||||
bool WritebackModeSupport;
|
||||
bool Writeback10bpc420Supported;
|
||||
bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
|
||||
unsigned int TotalNumberOfActiveWriteback;
|
||||
double CriticalPoint;
|
||||
double ReturnBWToDCNPerState;
|
||||
double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
|
||||
double ReturnBWPerState[DC__VOLTAGE_STATES + 1];
|
||||
double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
|
||||
bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
bool PrefetchSupported[DC__VOLTAGE_STATES + 1];
|
||||
bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1];
|
||||
bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1];
|
||||
bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1];
|
||||
bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1];
|
||||
bool ModeSupport[DC__VOLTAGE_STATES + 1];
|
||||
bool DIOSupport[DC__VOLTAGE_STATES + 1];
|
||||
bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
|
||||
bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
|
||||
bool ROBSupport[DC__VOLTAGE_STATES + 1];
|
||||
bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1];
|
||||
bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
bool IsErrorResult[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
|
||||
bool prefetch_vm_bw_valid;
|
||||
bool prefetch_row_bw_valid;
|
||||
bool NumberOfOTGSupport;
|
||||
bool NonsupportedDSCInputBPC;
|
||||
bool WritebackScaleRatioAndTapsSupport;
|
||||
bool CursorSupport;
|
||||
bool PitchSupport;
|
||||
|
||||
double WritebackLineBufferLumaBufferSize;
|
||||
double WritebackLineBufferChromaBufferSize;
|
||||
double WritebackMinHSCLRatio;
|
||||
double WritebackMinVSCLRatio;
|
||||
double WritebackMaxHSCLRatio;
|
||||
double WritebackMaxVSCLRatio;
|
||||
double WritebackMaxHSCLTaps;
|
||||
double WritebackMaxVSCLTaps;
|
||||
unsigned int MaxNumDPP;
|
||||
unsigned int MaxNumOTG;
|
||||
double CursorBufferSize;
|
||||
double CursorChunkSize;
|
||||
unsigned int Mode;
|
||||
unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double OutputLinkDPLanes[DC__NUM_DPP__MAX];
|
||||
double SwathWidthYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double SwathHeightYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double SwathHeightCPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double VRatioPreY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double VRatioPreC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double RequiredPrefetchPixelDataBW[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double RequiredDISPCLK[DC__VOLTAGE_STATES + 1];
|
||||
double TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1];
|
||||
double TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1];
|
||||
double PrefetchBW[DC__NUM_DPP__MAX];
|
||||
double PDEAndMetaPTEBytesPerFrame[DC__NUM_DPP__MAX];
|
||||
double MetaRowBytes[DC__NUM_DPP__MAX];
|
||||
double DPTEBytesPerRow[DC__NUM_DPP__MAX];
|
||||
double PrefetchLinesY[DC__NUM_DPP__MAX];
|
||||
double PrefetchLinesC[DC__NUM_DPP__MAX];
|
||||
unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
|
||||
unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
|
||||
double PrefillY[DC__NUM_DPP__MAX];
|
||||
double PrefillC[DC__NUM_DPP__MAX];
|
||||
double LineTimesForPrefetch[DC__NUM_DPP__MAX];
|
||||
double LinesForMetaPTE[DC__NUM_DPP__MAX];
|
||||
double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
|
||||
double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
|
||||
double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
unsigned int OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
|
||||
unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
|
||||
unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
|
||||
double MaxSwathHeightY[DC__NUM_DPP__MAX];
|
||||
double MaxSwathHeightC[DC__NUM_DPP__MAX];
|
||||
double MinSwathHeightY[DC__NUM_DPP__MAX];
|
||||
double MinSwathHeightC[DC__NUM_DPP__MAX];
|
||||
double PSCL_FACTOR[DC__NUM_DPP__MAX];
|
||||
double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
|
||||
double MaximumVStartup[DC__NUM_DPP__MAX];
|
||||
double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
|
||||
double AlignedYPitch[DC__NUM_DPP__MAX];
|
||||
double AlignedCPitch[DC__NUM_DPP__MAX];
|
||||
double MaximumSwathWidth[DC__NUM_DPP__MAX];
|
||||
double final_flip_bw[DC__NUM_DPP__MAX];
|
||||
double ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1];
|
||||
|
||||
double WritebackLumaVExtra;
|
||||
double WritebackChromaVExtra;
|
||||
double WritebackRequiredDISPCLK;
|
||||
double MaximumSwathWidthSupport;
|
||||
double MaximumSwathWidthInDETBuffer;
|
||||
double MaximumSwathWidthInLineBuffer;
|
||||
double MaxDispclkRoundedDownToDFSGranularity;
|
||||
double MaxDppclkRoundedDownToDFSGranularity;
|
||||
double PlaneRequiredDISPCLKWithoutODMCombine;
|
||||
double PlaneRequiredDISPCLK;
|
||||
double TotalNumberOfActiveOTG;
|
||||
double FECOverhead;
|
||||
double EffectiveFECOverhead;
|
||||
unsigned int Outbpp;
|
||||
unsigned int OutbppDSC;
|
||||
double TotalDSCUnitsRequired;
|
||||
double bpp;
|
||||
unsigned int slices;
|
||||
double SwathWidthGranularityY;
|
||||
double RoundedUpMaxSwathSizeBytesY;
|
||||
double SwathWidthGranularityC;
|
||||
double RoundedUpMaxSwathSizeBytesC;
|
||||
double LinesInDETLuma;
|
||||
double LinesInDETChroma;
|
||||
double EffectiveDETLBLinesLuma;
|
||||
double EffectiveDETLBLinesChroma;
|
||||
double ProjectedDCFCLKDeepSleep;
|
||||
double PDEAndMetaPTEBytesPerFrameY;
|
||||
double PDEAndMetaPTEBytesPerFrameC;
|
||||
unsigned int MetaRowBytesY;
|
||||
unsigned int MetaRowBytesC;
|
||||
unsigned int DPTEBytesPerRowC;
|
||||
unsigned int DPTEBytesPerRowY;
|
||||
double ExtraLatency;
|
||||
double TimeCalc;
|
||||
double TWait;
|
||||
double MaximumReadBandwidthWithPrefetch;
|
||||
double total_dcn_read_bw_with_flip;
|
||||
};
|
||||
|
||||
#endif /* _DML2_DISPLAY_MODE_VBA_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,148 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DML2_DISPLAY_RQ_DLG_CALC_H__
|
||||
#define __DML2_DISPLAY_RQ_DLG_CALC_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
// Function: dml_rq_dlg_get_rq_params
|
||||
// Calculate requestor related parameters that register definition agnostic
|
||||
// (i.e. this layer does try to separate real values from register definition)
|
||||
// Input:
|
||||
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
// Output:
|
||||
// rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
|
||||
//
|
||||
void dml_rq_dlg_get_rq_params(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_rq_params_st *rq_param,
|
||||
const display_pipe_source_params_st pipe_src_param);
|
||||
|
||||
// Function: dml_rq_dlg_get_rq_reg
|
||||
// Main entry point for test to get the register values out of this DML class.
|
||||
// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
|
||||
// and then populate the rq_regs struct
|
||||
// Input:
|
||||
// pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
|
||||
// Output:
|
||||
// rq_regs - struct that holds all the RQ registers field value.
|
||||
// See also: <display_rq_regs_st>
|
||||
void dml_rq_dlg_get_rq_reg(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_rq_regs_st *rq_regs,
|
||||
const display_pipe_source_params_st pipe_src_param);
|
||||
|
||||
// Function: dml_rq_dlg_get_dlg_params
|
||||
// Calculate deadline related parameters
|
||||
//
|
||||
void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx,
|
||||
display_dlg_regs_st *disp_dlg_regs,
|
||||
display_ttu_regs_st *disp_ttu_regs,
|
||||
const display_rq_dlg_params_st rq_dlg_param,
|
||||
const display_dlg_sys_params_st dlg_sys_param,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en,
|
||||
const bool ignore_viewport_pos,
|
||||
const bool immediate_flip_support);
|
||||
|
||||
// Function: dml_rq_dlg_get_dlg_param_prefetch
|
||||
// For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
|
||||
// for ALL pipes and use this info to calculate the prefetch programming.
|
||||
// Output: prefetch_param.prefetch_bw and flip_bytes
|
||||
void dml_rq_dlg_get_dlg_params_prefetch(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_dlg_prefetch_param_st *prefetch_param,
|
||||
display_rq_dlg_params_st rq_dlg_param,
|
||||
display_dlg_sys_params_st dlg_sys_param,
|
||||
display_e2e_pipe_params_st e2e_pipe_param,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en);
|
||||
|
||||
// Function: dml_rq_dlg_get_dlg_reg
|
||||
// Calculate and return DLG and TTU register struct given the system setting
|
||||
// Output:
|
||||
// dlg_regs - output DLG register struct
|
||||
// ttu_regs - output DLG TTU register struct
|
||||
// Input:
|
||||
// e2e_pipe_param - "compacted" array of e2e pipe param struct
|
||||
// num_pipes - num of active "pipe" or "route"
|
||||
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
|
||||
// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
|
||||
// Added for legacy or unrealistic timing tests.
|
||||
void dml_rq_dlg_get_dlg_reg(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_dlg_regs_st *dlg_regs,
|
||||
display_ttu_regs_st *ttu_regs,
|
||||
display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx,
|
||||
const bool cstate_en,
|
||||
const bool pstate_en,
|
||||
const bool vm_en,
|
||||
const bool ignore_viewport_pos,
|
||||
const bool immediate_flip_support);
|
||||
|
||||
// Function: dml_rq_dlg_get_calculated_vstartup
|
||||
// Calculate and return vstartup
|
||||
// Output:
|
||||
// unsigned int vstartup
|
||||
// Input:
|
||||
// e2e_pipe_param - "compacted" array of e2e pipe param struct
|
||||
// num_pipes - num of active "pipe" or "route"
|
||||
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
|
||||
// NOTE: this MUST be called after setting the prefetch mode!
|
||||
unsigned int dml_rq_dlg_get_calculated_vstartup(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx);
|
||||
|
||||
// Function: dml_rq_dlg_get_row_heights
|
||||
// Calculate dpte and meta row heights
|
||||
void dml_rq_dlg_get_row_heights(
|
||||
struct display_mode_lib *mode_lib,
|
||||
unsigned int *o_dpte_row_height,
|
||||
unsigned int *o_meta_row_height,
|
||||
unsigned int vp_width,
|
||||
unsigned int data_pitch,
|
||||
int source_format,
|
||||
int tiling,
|
||||
int macro_tile_size,
|
||||
int source_scan,
|
||||
int is_chroma);
|
||||
|
||||
// Function: dml_rq_dlg_get_arb_params
|
||||
void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param);
|
||||
|
||||
#endif
|
||||
|
|
@ -27,10 +27,11 @@
|
|||
#define __DISPLAY_RQ_DLG_CALC_H__
|
||||
|
||||
#include "dml_common_defs.h"
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
struct display_mode_lib;
|
||||
|
||||
#include "display_rq_dlg_helpers.h"
|
||||
|
||||
void dml1_extract_rq_regs(
|
||||
struct display_mode_lib *mode_lib,
|
||||
struct _vcs_dpi_display_rq_regs_st *rq_regs,
|
||||
|
|
|
|||
Loading…
Reference in New Issue