scsi: ufs: ufs-exynos: Add EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR option
To skip exynos_ufs_config_phy_*_attr settings for exynos-ufs variant, provide EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR as an opts flag. For the ExynosAuto v9 SoC's controller, M-Phy timing setting is not required and most of vendor-specific configuration will be performed in the pre_link callback function. Link: https://lore.kernel.org/r/20211018124216.153072-9-chanho61.park@samsung.com Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Kiwoong Kim <kwmad.kim@samsung.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -830,8 +830,10 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
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/* m-phy */
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exynos_ufs_phy_init(ufs);
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exynos_ufs_config_phy_time_attr(ufs);
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exynos_ufs_config_phy_cap_attr(ufs);
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if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
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exynos_ufs_config_phy_time_attr(ufs);
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exynos_ufs_config_phy_cap_attr(ufs);
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}
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exynos_ufs_setup_clocks(hba, true, PRE_CHANGE);
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@ -199,6 +199,7 @@ struct exynos_ufs {
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#define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
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#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
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#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
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#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
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};
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#define for_each_ufs_rx_lane(ufs, i) \
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