drm/amdgpu: fix VCE ib alignment value

The VCE rings only require single dword alignment.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-08-23 10:44:16 -04:00
parent c4795ca642
commit a22f803cd2
1 changed files with 1 additions and 1 deletions

View File

@ -299,7 +299,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
ib_size_alignment = 8;
ib_size_alignment = 1;
break;
default:
return -EINVAL;