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drm/amdgpu: Constify tables 

Mark some powerplay tables as 'const' and adjust pointers acessing
them to avoid introducing warnings.

Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nils Wallménius 2016-09-22 21:13:49 +02:00 committed by Alex Deucher
parent beb86f29c9
commit a1c1a1de43
6 changed files with 20 additions and 21 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -4278,7 +4278,7 @@ static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type
return 0; return 0;
} }
static struct pp_hwmgr_func smu7_hwmgr_funcs = { static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init, .backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &phm_hwmgr_backend_fini, .backend_fini = &phm_hwmgr_backend_fini,
.asic_setup = &smu7_setup_asic_task, .asic_setup = &smu7_setup_asic_task,

12
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
View File

@ -31,7 +31,7 @@
static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; static uint32_t DIDTBlock_Info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = { static const struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
* Offset Mask Shift Value Type * Offset Mask Shift Value Type
* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@ -62,7 +62,7 @@ static struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
{ 0xFFFFFFFF } { 0xFFFFFFFF }
}; };
static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = { static const struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
* Offset Mask Shift Value Type * Offset Mask Shift Value Type
* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@ -93,7 +93,7 @@ static struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
{ 0xFFFFFFFF } { 0xFFFFFFFF }
}; };
static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = { static const struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
* Offset Mask Shift Value Type * Offset Mask Shift Value Type
* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@ -235,7 +235,7 @@ static struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
{ 0xFFFFFFFF } { 0xFFFFFFFF }
}; };
static struct gpu_pt_config_reg DIDTConfig_Polaris11[] = { static const struct gpu_pt_config_reg DIDTConfig_Polaris11[] = {
/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
* Offset Mask Shift Value Type * Offset Mask Shift Value Type
* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@ -427,9 +427,9 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
} }
static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr, static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
struct gpu_pt_config_reg *cac_config_regs) const struct gpu_pt_config_reg *cac_config_regs)
{ {
struct gpu_pt_config_reg *config_regs = cac_config_regs; const struct gpu_pt_config_reg *config_regs = cac_config_regs;
uint32_t cache = 0; uint32_t cache = 0;
uint32_t data = 0; uint32_t data = 0;

10
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
View File

@ -63,7 +63,7 @@
#define DEVICE_ID_VI_ICELAND_M_6902 0x6902 #define DEVICE_ID_VI_ICELAND_M_6902 0x6902
#define DEVICE_ID_VI_ICELAND_M_6903 0x6903 #define DEVICE_ID_VI_ICELAND_M_6903 0x6903
static struct iceland_pt_defaults defaults_iceland = { static const struct iceland_pt_defaults defaults_iceland = {
/* /*
* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
@ -74,7 +74,7 @@ static struct iceland_pt_defaults defaults_iceland = {
}; };
/* 35W - XT, XTL */ /* 35W - XT, XTL */
static struct iceland_pt_defaults defaults_icelandxt = { static const struct iceland_pt_defaults defaults_icelandxt = {
/* /*
* sviLoadLIneEn, SviLoadLineVddC, * sviLoadLIneEn, SviLoadLineVddC,
* TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
@ -87,7 +87,7 @@ static struct iceland_pt_defaults defaults_icelandxt = {
}; };
/* 25W - PRO, LE */ /* 25W - PRO, LE */
static struct iceland_pt_defaults defaults_icelandpro = { static const struct iceland_pt_defaults defaults_icelandpro = {
/* /*
* sviLoadLIneEn, SviLoadLineVddC, * sviLoadLIneEn, SviLoadLineVddC,
* TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
@ -1740,11 +1740,11 @@ static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{ {
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults; const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table; struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table; struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
uint16_t *def1, *def2; const uint16_t *def1, *def2;
int i, j, k; int i, j, k;

2
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h
View File

@ -62,7 +62,7 @@ struct iceland_smumgr {
struct SMU71_Discrete_DpmTable smc_state_table; struct SMU71_Discrete_DpmTable smc_state_table;
struct SMU71_Discrete_PmFuses power_tune_table; struct SMU71_Discrete_PmFuses power_tune_table;
struct SMU71_Discrete_Ulv ulv_setting; struct SMU71_Discrete_Ulv ulv_setting;
struct iceland_pt_defaults *power_tune_defaults; const struct iceland_pt_defaults *power_tune_defaults;
SMU71_Discrete_MCRegisters mc_regs; SMU71_Discrete_MCRegisters mc_regs;
struct iceland_mc_reg_table mc_reg_table; struct iceland_mc_reg_table mc_reg_table;
uint32_t activity_target[SMU71_MAX_LEVELS_GRAPHICS]; uint32_t activity_target[SMU71_MAX_LEVELS_GRAPHICS];

13
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
View File

@ -58,7 +58,7 @@
#define VDDC_VDDCI_DELTA 200 #define VDDC_VDDCI_DELTA 200
static struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
* TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
*/ */
@ -1815,14 +1815,13 @@ static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{ {
struct tonga_smumgr *smu_data = struct tonga_smumgr *smu_data =
(struct tonga_smumgr *)(hwmgr->smumgr->backend); (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
int i, j, k; int i, j, k;
uint16_t *pdef1; const uint16_t *pdef1, *pdef2;
uint16_t *pdef2;
dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
(uint16_t)(cac_dtp_table->usTDP * 256)); (uint16_t)(cac_dtp_table->usTDP * 256));
@ -1863,7 +1862,7 @@ static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
{ {
struct tonga_smumgr *smu_data = struct tonga_smumgr *smu_data =
(struct tonga_smumgr *)(hwmgr->smumgr->backend); (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC; smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
@ -1878,7 +1877,7 @@ static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
uint16_t tdc_limit; uint16_t tdc_limit;
struct tonga_smumgr *smu_data = struct tonga_smumgr *smu_data =
(struct tonga_smumgr *)(hwmgr->smumgr->backend); (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
struct phm_ppt_v1_information *table_info = struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable); (struct phm_ppt_v1_information *)(hwmgr->pptable);
@ -1899,7 +1898,7 @@ static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset
{ {
struct tonga_smumgr *smu_data = struct tonga_smumgr *smu_data =
(struct tonga_smumgr *)(hwmgr->smumgr->backend); (struct tonga_smumgr *)(hwmgr->smumgr->backend);
struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp; uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr, if (smu7_read_smc_sram_dword(hwmgr->smumgr,

2
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h
View File

@ -48,7 +48,7 @@ struct tonga_smumgr {
struct SMU72_Discrete_DpmTable smc_state_table; struct SMU72_Discrete_DpmTable smc_state_table;
struct SMU72_Discrete_Ulv ulv_setting; struct SMU72_Discrete_Ulv ulv_setting;
struct SMU72_Discrete_PmFuses power_tune_table; struct SMU72_Discrete_PmFuses power_tune_table;
struct tonga_pt_defaults *power_tune_defaults; const struct tonga_pt_defaults *power_tune_defaults;
SMU72_Discrete_MCRegisters mc_regs; SMU72_Discrete_MCRegisters mc_regs;
struct tonga_mc_reg_table mc_reg_table; struct tonga_mc_reg_table mc_reg_table;