drm/amd/powerplay: use true, false for bool variable in smu7_hwmgr.c
Fixes coccicheck warning: drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:723:2-50: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:733:3-52: WARNING: Assignment of 0/1 to bool variable drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:747:3-51: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: zhengbin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -720,7 +720,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
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data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
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data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
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/* param1 is for corresponding std voltage */
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data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
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data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
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}
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data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
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@ -730,7 +730,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
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/* Initialize Vddci DPM table based on allow Mclk values */
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for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
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data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
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data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
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data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
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}
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data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
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}
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@ -744,7 +744,7 @@ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
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*/
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for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
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data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
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data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
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data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
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}
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data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
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}
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