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powerpc/8xx: drop unused self-modifying code alternative to FixupDAR. 

The code which fixups the DAR on TLB errors for dbcX instructions
has a self-modifying code alternative that has never been used.

Drop it.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b095e12c82fcba1ac4c09fc3b85d969f36614746.1566417610.git.christophe.leroy@c-s.fr
This commit is contained in:
Christophe Leroy 2019-08-21 20:00:34 +00:00 committed by Michael Ellerman
parent 63ce271b5e
commit a045657412
1 changed files with 0 additions and 24 deletions
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24
arch/powerpc/kernel/head_8xx.S
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@ -574,8 +574,6 @@ InstructionBreakpoint:
* by decoding the registers used by the dcbx instruction and adding them. * by decoding the registers used by the dcbx instruction and adding them.
* DAR is set to the calculated address. * DAR is set to the calculated address.
*/ */
/* define if you don't want to use self modifying code */
#define NO_SELF_MODIFYING_CODE
FixupDAR:/* Entry point for dcbx workaround. */ FixupDAR:/* Entry point for dcbx workaround. */
mtspr SPRN_M_TW, r10 mtspr SPRN_M_TW, r10
/* fetch instruction from memory. */ /* fetch instruction from memory. */
@ -639,27 +637,6 @@ FixupDAR:/* Entry point for dcbx workaround. */
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
mtspr SPRN_DSISR, r10 mtspr SPRN_DSISR, r10
142: /* continue, it was a dcbx, dcbi instruction. */ 142: /* continue, it was a dcbx, dcbi instruction. */
#ifndef NO_SELF_MODIFYING_CODE
andis. r10,r11,0x1f /* test if reg RA is r0 */
li r10,modified_instr@l
dcbtst r0,r10 /* touch for store */
rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
ori r11,r11,532
stw r11,0(r10) /* store add/and instruction */
dcbf 0,r10 /* flush new instr. to memory. */
icbi 0,r10 /* invalidate instr. cache line */
mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
isync /* Wait until new instr is loaded from memory */
modified_instr:
.space 4 /* this is where the add instr. is stored */
bne+ 143f
subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
143: mtdar r10 /* store faulting EA in DAR */
mfspr r10,SPRN_M_TW
b DARFixed /* Go back to normal TLB handling */
#else
mfctr r10 mfctr r10
mtdar r10 /* save ctr reg in DAR */ mtdar r10 /* save ctr reg in DAR */
rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
@ -723,7 +700,6 @@ modified_instr:
add r10, r10, r11 /* add it */ add r10, r10, r11 /* add it */
mfctr r11 /* restore r11 */ mfctr r11 /* restore r11 */
b 151b b 151b
#endif
/* /*
* This is where the main kernel code starts. * This is where the main kernel code starts.