spi: tegra114: dump SPI registers during timeout
This patch dumps SPI registers on transfer error or timeout for debug purpose. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -874,6 +874,20 @@ static void tegra_spi_transfer_end(struct spi_device *spi)
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tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
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}
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static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
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{
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dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
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dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
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tegra_spi_readl(tspi, SPI_COMMAND1),
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tegra_spi_readl(tspi, SPI_COMMAND2));
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dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
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tegra_spi_readl(tspi, SPI_DMA_CTL),
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tegra_spi_readl(tspi, SPI_DMA_BLK));
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dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
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tegra_spi_readl(tspi, SPI_TRANS_STATUS),
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tegra_spi_readl(tspi, SPI_FIFO_STATUS));
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}
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static int tegra_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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@ -920,6 +934,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
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(tspi->cur_direction & DATA_DIR_RX))
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dmaengine_terminate_all(tspi->rx_dma_chan);
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ret = -EIO;
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tegra_spi_dump_regs(tspi);
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tegra_spi_flush_fifos(tspi);
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reset_control_assert(tspi->rst);
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udelay(2);
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@ -930,6 +945,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
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if (tspi->tx_status || tspi->rx_status) {
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dev_err(tspi->dev, "Error in Transfer\n");
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ret = -EIO;
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tegra_spi_dump_regs(tspi);
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goto complete_xfer;
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}
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msg->actual_length += xfer->len;
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@ -971,6 +987,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
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tspi->status_reg);
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dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
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tspi->command1_reg, tspi->dma_control_reg);
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tegra_spi_dump_regs(tspi);
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tegra_spi_flush_fifos(tspi);
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complete(&tspi->xfer_completion);
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spin_unlock_irqrestore(&tspi->lock, flags);
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@ -1045,6 +1062,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
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tspi->status_reg);
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dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
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tspi->command1_reg, tspi->dma_control_reg);
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tegra_spi_dump_regs(tspi);
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tegra_spi_flush_fifos(tspi);
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complete(&tspi->xfer_completion);
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spin_unlock_irqrestore(&tspi->lock, flags);
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