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rtw89: update ptcl_init 

ptcl_init, standing for protocol initialization, is updated to the latest
version.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-17-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2022-03-25 14:00:55 +08:00 committed by Kalle Valo
parent 75fd91aa92
commit 9fb4862e91
2 changed files with 39 additions and 5 deletions
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20
drivers/net/wireless/realtek/rtw89/mac.c
View File

@ -2065,6 +2065,8 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
val = rtw89_read32(rtwdev, reg);
val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK);
val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
val |= B_AX_HW_CTS2SELF_EN;
rtw89_write32(rtwdev, reg, val);
@ -2075,11 +2077,19 @@ static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
rtw89_write32(rtwdev, reg, val);
}
reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx);
val = rtw89_read32(rtwdev, reg);
val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
val |= B_AX_HW_CTS2SELF_EN;
rtw89_write32(rtwdev, reg, val);
if (mac_idx == RTW89_MAC_0) {
rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1);
rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
B_AX_PTCL_TRIGGER_SS_EN_0 |
B_AX_PTCL_TRIGGER_SS_EN_1 |
B_AX_PTCL_TRIGGER_SS_EN_UL);
rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
} else if (mac_idx == RTW89_MAC_1) {
rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
}
return 0;
}

24
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -1248,6 +1248,18 @@
#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
#define R_AX_PTCL_COMMON_SETTING_0 0xC600
#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600
#define B_AX_PCIE_MODE_MASK GENMASK(15, 14)
#define B_AX_CPUMGQ_LIFETIME_EN BIT(8)
#define B_AX_MGQ_LIFETIME_EN BIT(7)
#define B_AX_LIFETIME_EN BIT(6)
#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4)
#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3)
#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2)
#define B_AX_CMAC_TX_MODE_1 BIT(1)
#define B_AX_CMAC_TX_MODE_0 BIT(0)
#define R_AX_AMPDU_AGG_LIMIT 0xC610
#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
@ -1292,6 +1304,18 @@
#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16)
#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
#define R_AX_PTCLRPT_FULL_HDL 0xC660
#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660
#define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12)
#define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
#define B_AX_F2PCMD_RPT_EN BIT(8)
#define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6)
#define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4)
#define FWD_TO_WLCPU 1
#define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2)
#define B_AX_F2PCMDRPT_FULL_DROP BIT(1)
#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0)
#define R_AX_BT_PLT 0xC67C
#define R_AX_BT_PLT_C1 0xE67C
#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16)