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drm/radeon: fix render backend setup for SI and CIK 

Only the render backends of the first shader engine were enabled. The others
were erroneously disabled. Enabling the other render backends improves
performance a lot.

Unigine Sanctuary on Bonaire:
  Before: 15 fps
  After:  90 fps

Judging from the fan noise, the GPU was also underclocked when the other
render backends were disabled, resulting in horrible performance. The fan is
a lot noisy under load now.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Marek Olšák 2013-12-22 02:18:00 +01:00 committed by Alex Deucher
parent d00adcc8ae
commit 9fadb352ed
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/radeon/cik.c
View File

@ -3057,7 +3057,7 @@ static u32 cik_create_bitmask(u32 bit_width)
* Returns the disabled RB bitmask. * Returns the disabled RB bitmask.
*/ */
static u32 cik_get_rb_disabled(struct radeon_device *rdev, static u32 cik_get_rb_disabled(struct radeon_device *rdev,
u32 max_rb_num, u32 se_num, u32 max_rb_num_per_se,
u32 sh_per_se) u32 sh_per_se)
{ {
u32 data, mask; u32 data, mask;
@ -3071,7 +3071,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
data >>= BACKEND_DISABLE_SHIFT; data >>= BACKEND_DISABLE_SHIFT;
mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se); mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
return data & mask; return data & mask;
} }
@ -3088,7 +3088,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
*/ */
static void cik_setup_rb(struct radeon_device *rdev, static void cik_setup_rb(struct radeon_device *rdev,
u32 se_num, u32 sh_per_se, u32 se_num, u32 sh_per_se,
u32 max_rb_num) u32 max_rb_num_per_se)
{ {
int i, j; int i, j;
u32 data, mask; u32 data, mask;
@ -3098,7 +3098,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
for (i = 0; i < se_num; i++) { for (i = 0; i < se_num; i++) {
for (j = 0; j < sh_per_se; j++) { for (j = 0; j < sh_per_se; j++) {
cik_select_se_sh(rdev, i, j); cik_select_se_sh(rdev, i, j);
data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
if (rdev->family == CHIP_HAWAII) if (rdev->family == CHIP_HAWAII)
disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH); disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
else else
@ -3108,7 +3108,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
mask = 1; mask = 1;
for (i = 0; i < max_rb_num; i++) { for (i = 0; i < max_rb_num_per_se * se_num; i++) {
if (!(disabled_rbs & mask)) if (!(disabled_rbs & mask))
enabled_rbs |= mask; enabled_rbs |= mask;
mask <<= 1; mask <<= 1;

10
drivers/gpu/drm/radeon/si.c
View File

@ -2811,7 +2811,7 @@ static void si_setup_spi(struct radeon_device *rdev,
} }
static u32 si_get_rb_disabled(struct radeon_device *rdev, static u32 si_get_rb_disabled(struct radeon_device *rdev,
u32 max_rb_num, u32 se_num, u32 max_rb_num_per_se,
u32 sh_per_se) u32 sh_per_se)
{ {
u32 data, mask; u32 data, mask;
@ -2825,14 +2825,14 @@ static u32 si_get_rb_disabled(struct radeon_device *rdev,
data >>= BACKEND_DISABLE_SHIFT; data >>= BACKEND_DISABLE_SHIFT;
mask = si_create_bitmask(max_rb_num / se_num / sh_per_se); mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
return data & mask; return data & mask;
} }
static void si_setup_rb(struct radeon_device *rdev, static void si_setup_rb(struct radeon_device *rdev,
u32 se_num, u32 sh_per_se, u32 se_num, u32 sh_per_se,
u32 max_rb_num) u32 max_rb_num_per_se)
{ {
int i, j; int i, j;
u32 data, mask; u32 data, mask;
@ -2842,14 +2842,14 @@ static void si_setup_rb(struct radeon_device *rdev,
for (i = 0; i < se_num; i++) { for (i = 0; i < se_num; i++) {
for (j = 0; j < sh_per_se; j++) { for (j = 0; j < sh_per_se; j++) {
si_select_se_sh(rdev, i, j); si_select_se_sh(rdev, i, j);
data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
} }
} }
si_select_se_sh(rdev, 0xffffffff, 0xffffffff); si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
mask = 1; mask = 1;
for (i = 0; i < max_rb_num; i++) { for (i = 0; i < max_rb_num_per_se * se_num; i++) {
if (!(disabled_rbs & mask)) if (!(disabled_rbs & mask))
enabled_rbs |= mask; enabled_rbs |= mask;
mask <<= 1; mask <<= 1;