ath10k: wmi: get wmi init parameter values from hw params
The parameter values for skid limit, number of peers and wds entries values which are sent in wmi init cmd are hardware specific. Add support to obtain skid limit, number of peers and wds entries values from hw params which will have the hw specific values for these parameters. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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1807da4973
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@ -75,6 +75,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9887_HW_1_0_VERSION,
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.id = QCA9887_HW_1_0_VERSION,
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@ -99,6 +102,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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@ -122,6 +128,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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@ -145,6 +154,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_3_0_VERSION,
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.id = QCA6174_HW_3_0_VERSION,
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@ -168,6 +180,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_3_2_VERSION,
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.id = QCA6174_HW_3_2_VERSION,
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@ -194,6 +209,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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@ -223,6 +241,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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.id = QCA9984_HW_1_0_DEV_VERSION,
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@ -257,6 +278,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 1560,
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.vht160_mcs_rx_highest = 1560,
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.vht160_mcs_tx_highest = 1560,
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.vht160_mcs_tx_highest = 1560,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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.id = QCA9888_HW_2_0_DEV_VERSION,
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@ -290,6 +314,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 780,
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.vht160_mcs_rx_highest = 780,
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.vht160_mcs_tx_highest = 780,
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.vht160_mcs_tx_highest = 780,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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.id = QCA9377_HW_1_0_DEV_VERSION,
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@ -313,6 +340,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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.id = QCA9377_HW_1_1_DEV_VERSION,
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@ -338,6 +368,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@ -368,6 +401,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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},
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},
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};
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};
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@ -553,6 +553,10 @@ struct ath10k_hw_params {
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/* Number of ciphers supported (i.e First N) in cipher_suites array */
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/* Number of ciphers supported (i.e First N) in cipher_suites array */
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int n_cipher_suites;
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int n_cipher_suites;
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u32 num_peers;
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u32 ast_skid_limit;
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u32 num_wds_entries;
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};
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};
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struct htt_rx_desc;
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struct htt_rx_desc;
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@ -1439,7 +1439,10 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
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cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks);
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cmd->num_host_mem_chunks = __cpu_to_le32(ar->wmi.num_mem_chunks);
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cfg->num_vdevs = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
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cfg->num_vdevs = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
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cfg->num_peers = __cpu_to_le32(TARGET_TLV_NUM_PEERS);
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cfg->num_peers = __cpu_to_le32(ar->hw_params.num_peers);
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cfg->ast_skid_limit = __cpu_to_le32(ar->hw_params.ast_skid_limit);
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cfg->num_wds_entries = __cpu_to_le32(ar->hw_params.num_wds_entries);
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if (test_bit(WMI_SERVICE_RX_FULL_REORDER, ar->wmi.svc_map)) {
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if (test_bit(WMI_SERVICE_RX_FULL_REORDER, ar->wmi.svc_map)) {
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cfg->num_offload_peers = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
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cfg->num_offload_peers = __cpu_to_le32(TARGET_TLV_NUM_VDEVS);
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@ -1451,7 +1454,6 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
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cfg->num_peer_keys = __cpu_to_le32(2);
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cfg->num_peer_keys = __cpu_to_le32(2);
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cfg->num_tids = __cpu_to_le32(TARGET_TLV_NUM_TIDS);
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cfg->num_tids = __cpu_to_le32(TARGET_TLV_NUM_TIDS);
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cfg->ast_skid_limit = __cpu_to_le32(0x10);
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cfg->tx_chain_mask = __cpu_to_le32(0x7);
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cfg->tx_chain_mask = __cpu_to_le32(0x7);
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cfg->rx_chain_mask = __cpu_to_le32(0x7);
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cfg->rx_chain_mask = __cpu_to_le32(0x7);
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cfg->rx_timeout_pri[0] = __cpu_to_le32(0x64);
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cfg->rx_timeout_pri[0] = __cpu_to_le32(0x64);
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@ -1467,7 +1469,6 @@ static struct sk_buff *ath10k_wmi_tlv_op_gen_init(struct ath10k *ar)
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cfg->num_mcast_table_elems = __cpu_to_le32(0);
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cfg->num_mcast_table_elems = __cpu_to_le32(0);
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cfg->mcast2ucast_mode = __cpu_to_le32(0);
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cfg->mcast2ucast_mode = __cpu_to_le32(0);
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cfg->tx_dbg_log_size = __cpu_to_le32(0x400);
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cfg->tx_dbg_log_size = __cpu_to_le32(0x400);
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cfg->num_wds_entries = __cpu_to_le32(0x20);
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cfg->dma_burst_size = __cpu_to_le32(0);
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cfg->dma_burst_size = __cpu_to_le32(0);
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cfg->mac_aggr_delim = __cpu_to_le32(0);
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cfg->mac_aggr_delim = __cpu_to_le32(0);
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cfg->rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(0);
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cfg->rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(0);
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