- Allwinner A100 DMA node
- Allwinner H6 GPU devfreq scaling - sunxi sram bindings cleanup and D1 addition -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCYyeLcAAKCRB0Ba7+DO8k k29tAQDWg16eBX+DxH0QiTSvAOU8Baq1auW9+wHWjbP9KEaI+gD/XlYpHQcX2FME ck+BP47ZeWInvt0vv2/HlRVOOsHEIQM= =v2pD -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmMtwCAACgkQmmx57+YA GNlLnA/8CbdEp1FGj5tHdt9vFu0Zof/2PIhWk4ACq8fIAq7zvb2uwVINU0ZuNlBy yEWU2nka9P00MySmI/yVuf1zuPV8pT3BgXjEby32+KKrz1lAGORgQpOwe8UuxHVg ieCR2UH0MTfpfAIuRr4XLN/M72QJS7STaSP62N2ZF1txosbE14Xf/Mv5lCHUiAuG YYZtcqdikpBsdy6nHaZMyqA7dTYcJhzmTuvnYKaa9QJXdgFzshmqlWVjCsTZ1x5l I06x2otj8S5DU9nIWi66nuEHduRFk6UrSvRD7O5DpPSK1RKtNQlofjldRQw+qf96 qp9qcA0hQ7nOst6cUfFhgQW0IeTxJ0GXUpgHNPeNLxVhdpOcRkr9y3gEFlu/xyEk 667zJ3E1tTpmExVVaE3uQ1va0md+cb0tJB/Kqw6abpcmdyTf4s9Nb2znV93GiyBe O1Um1ItLX8g1l5oInm52wklQhQD2v849oF9KXBkPl6IBVcw/sfKQ3amLOaVHfqLb Oti+7kWAOx71cLna1Ma7TWxhTCtROOBbM/NaRhht7A0ficnU8yDn1u0rW9kx1gKv kgtPCoftnozcIJUjRd0ArcCPkAd18XZvFespbPS3txgkfJFvECEQ2rZDFp6ZE1wz wCrfGGWngxsVEYNIkkvvjSGARevC9Ft+YJhkaDtWTkmE3ylL2+w= =DYkD -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt - Allwinner A100 DMA node - Allwinner H6 GPU devfreq scaling - sunxi sram bindings cleanup and D1 addition * tag 'sunxi-dt-for-6.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: dt-bindings: sram: sunxi-sram: Add D1 compatible string dt-bindings: sram: sunxi-sram: Clean up the compatible lists arm64: dts: allwinner: beelink-gs1: Enable GPU OPP arm64: dts: allwinner: h6: Add GPU OPP table arm64: dts: allwinner: h6: Add cooling map for GPU arm64: dts: allwinner: a100: Add I2C DMA requests arm64: dts: allwinner: a100: Add device node for DMA controller Link: https://lore.kernel.org/r/YyePKDnOeP8Tdt5n@kista.localdomain Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
9f1fe339ef
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@ -24,32 +24,31 @@ properties:
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compatible:
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oneOf:
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- const: allwinner,sun4i-a10-sram-controller
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- enum:
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- allwinner,sun4i-a10-sram-controller
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- allwinner,sun50i-a64-sram-controller
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deprecated: true
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- const: allwinner,sun4i-a10-system-control
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- const: allwinner,sun5i-a13-system-control
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- enum:
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- allwinner,sun4i-a10-system-control
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- allwinner,sun5i-a13-system-control
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- allwinner,sun8i-a23-system-control
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- allwinner,sun8i-h3-system-control
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- allwinner,sun20i-d1-system-control
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- allwinner,sun50i-a64-system-control
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- allwinner,sun50i-h5-system-control
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- allwinner,sun50i-h616-system-control
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- items:
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- const: allwinner,sun7i-a20-system-control
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- enum:
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- allwinner,suniv-f1c100s-system-control
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- allwinner,sun7i-a20-system-control
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- allwinner,sun8i-r40-system-control
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- const: allwinner,sun4i-a10-system-control
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- const: allwinner,sun8i-a23-system-control
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- const: allwinner,sun8i-h3-system-control
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- items:
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- const: allwinner,sun8i-v3s-system-control
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- const: allwinner,sun8i-h3-system-control
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- items:
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- const: allwinner,sun8i-r40-system-control
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- const: allwinner,sun4i-a10-system-control
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- const: allwinner,sun50i-a64-sram-controller
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deprecated: true
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- const: allwinner,sun50i-a64-system-control
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- const: allwinner,sun50i-h5-system-control
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- items:
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- const: allwinner,sun50i-h6-system-control
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- const: allwinner,sun50i-a64-system-control
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- items:
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- const: allwinner,suniv-f1c100s-system-control
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- const: allwinner,sun4i-a10-system-control
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- const: allwinner,sun50i-h616-system-control
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reg:
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maxItems: 1
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@ -76,43 +75,26 @@ patternProperties:
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- const: allwinner,sun4i-a10-sram-d
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- const: allwinner,sun50i-a64-sram-c
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- items:
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- const: allwinner,sun5i-a13-sram-a3-a4
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- enum:
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- allwinner,sun5i-a13-sram-a3-a4
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- allwinner,sun7i-a20-sram-a3-a4
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- const: allwinner,sun4i-a10-sram-a3-a4
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- items:
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- const: allwinner,sun7i-a20-sram-a3-a4
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- const: allwinner,sun4i-a10-sram-a3-a4
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- items:
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- const: allwinner,sun5i-a13-sram-c1
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- enum:
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- allwinner,sun5i-a13-sram-c1
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- allwinner,sun7i-a20-sram-c1
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- allwinner,sun8i-a23-sram-c1
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- allwinner,sun8i-h3-sram-c1
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- allwinner,sun8i-r40-sram-c1
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- allwinner,sun50i-a64-sram-c1
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- allwinner,sun50i-h5-sram-c1
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- allwinner,sun50i-h6-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun7i-a20-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun8i-a23-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun8i-h3-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun8i-r40-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun50i-a64-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun50i-h5-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun50i-h6-sram-c1
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- const: allwinner,sun4i-a10-sram-c1
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- items:
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- const: allwinner,sun5i-a13-sram-d
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- const: allwinner,sun4i-a10-sram-d
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- items:
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- const: allwinner,sun7i-a20-sram-d
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- const: allwinner,sun4i-a10-sram-d
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- items:
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- const: allwinner,suniv-f1c100s-sram-d
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- enum:
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- allwinner,suniv-f1c100s-sram-d
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- allwinner,sun5i-a13-sram-d
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- allwinner,sun7i-a20-sram-d
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- const: allwinner,sun4i-a10-sram-d
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- items:
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- const: allwinner,sun50i-h6-sram-c
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@ -101,6 +101,18 @@
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#reset-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun50i-a100-dma";
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reg = <0x03002000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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resets = <&ccu RST_BUS_DMA>;
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dma-channels = <8>;
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dma-requests = <52>;
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#dma-cells = <1>;
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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dmas = <&dma 43>, <&dma 43>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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dmas = <&dma 44>, <&dma 44>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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dmas = <&dma 45>, <&dma 45>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -248,6 +266,8 @@
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C3>;
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resets = <&ccu RST_BUS_I2C3>;
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dmas = <&dma 46>, <&dma 46>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -325,6 +345,8 @@
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB2_I2C0>;
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resets = <&r_ccu RST_R_APB2_I2C0>;
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dmas = <&dma 50>, <&dma 50>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&r_i2c0_pins>;
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status = "disabled";
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@ -340,6 +362,8 @@
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB2_I2C1>;
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resets = <&r_ccu RST_R_APB2_I2C1>;
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dmas = <&dma 51>, <&dma 51>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&r_i2c1_pins>;
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status = "disabled";
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@ -5,6 +5,7 @@
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#include "sun50i-h6.dtsi"
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#include "sun50i-h6-cpu-opp.dtsi"
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#include "sun50i-h6-gpu-opp.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@ -0,0 +1,87 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2022 Clément Péron <peron.clem@gmail.com>
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/ {
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gpu_opp_table: opp-table-gpu {
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compatible = "operating-points-v2";
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <810000 810000 1200000>;
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};
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opp-264000000 {
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opp-hz = /bits/ 64 <264000000>;
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opp-microvolt = <810000 810000 1200000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <810000 810000 1200000>;
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};
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opp-336000000 {
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opp-hz = /bits/ 64 <336000000>;
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opp-microvolt = <810000 810000 1200000>;
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};
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opp-360000000 {
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opp-hz = /bits/ 64 <360000000>;
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opp-microvolt = <820000 820000 1200000>;
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};
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opp-384000000 {
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opp-hz = /bits/ 64 <384000000>;
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opp-microvolt = <830000 830000 1200000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <840000 840000 1200000>;
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};
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opp-420000000 {
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opp-hz = /bits/ 64 <420000000>;
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opp-microvolt = <850000 850000 1200000>;
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};
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opp-432000000 {
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opp-hz = /bits/ 64 <432000000>;
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opp-microvolt = <860000 860000 1200000>;
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};
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opp-456000000 {
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opp-hz = /bits/ 64 <456000000>;
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opp-microvolt = <870000 870000 1200000>;
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <890000 890000 1200000>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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opp-microvolt = <910000 910000 1200000>;
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};
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opp-576000000 {
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opp-hz = /bits/ 64 <576000000>;
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opp-microvolt = <930000 930000 1200000>;
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};
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opp-624000000 {
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opp-hz = /bits/ 64 <624000000>;
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opp-microvolt = <950000 950000 1200000>;
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};
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opp-756000000 {
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opp-hz = /bits/ 64 <756000000>;
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opp-microvolt = <1040000 1040000 1200000>;
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};
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};
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};
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&gpu {
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operating-points-v2 = <&gpu_opp_table>;
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};
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@ -186,6 +186,7 @@
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clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
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clock-names = "core", "bus";
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resets = <&ccu RST_BUS_GPU>;
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#cooling-cells = <2>;
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status = "disabled";
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};
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@ -1072,9 +1073,55 @@
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};
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gpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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polling-delay-passive = <1000>;
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polling-delay = <2000>;
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thermal-sensors = <&ths 1>;
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trips {
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gpu_alert0: gpu-alert-0 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_alert1: gpu-alert-1 {
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temperature = <100000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_alert2: gpu-alert-2 {
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temperature = <105000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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// Forbid the GPU to go over 756MHz
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map0 {
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trip = <&gpu_alert0>;
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cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
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};
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// Forbid the GPU to go over 624MHz
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map1 {
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trip = <&gpu_alert1>;
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cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
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};
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// Forbid the GPU to go over 576MHz
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map2 {
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trip = <&gpu_alert2>;
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cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
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};
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};
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};
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||||
};
|
||||
};
|
||||
|
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Loading…
Reference in New Issue