ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand
LLVM's integrated assembler does not accept r15 as mrc operand. arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache ^ Use APSR_nzcv instead of r15. The GNU assembler supports this syntax since binutils 2.21 [0]. [0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076 Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -1273,7 +1273,7 @@ iflush:
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__armv5tej_mmu_cache_flush:
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tst r4, #1
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movne pc, lr
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
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bne 1b
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mcr p15, 0, r0, c7, c5, 0 @ flush I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all)
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mov ip, #0
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__flush_whole_cache:
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
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bne 1b
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#endif
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tst r2, #VM_EXEC
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@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
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bne 1b
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#endif
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#ifndef CONFIG_CPU_ICACHE_DISABLE
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@ -131,7 +131,7 @@ __flush_whole_cache:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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tst r2, #VM_EXEC
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@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm)
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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@ && 'Clean & Invalidate whole DCache'
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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