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drm/nouveau/gr/gm200: s/gm204/gm200/ 

Most of the per-chipset differences will go away when we fully switch
to using the register lists provided by the firmware files, which will
leave all the remaining code "belonging" to GM200.

This is a preemptive rename from GM204 to GM200.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2016-02-24 14:03:40 +10:00
parent e24c9c44d7
commit 9ec280529a
10 changed files with 128 additions and 128 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View File

@ -40,7 +40,7 @@ int gk110b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk208_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk20a_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm204_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm200_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm206_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm20b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
#endif

2
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2019,7 +2019,7 @@ nv124_chipset = {
.disp = gm200_disp_new,
.dma = gf119_dma_new,
.fifo = gm200_fifo_new,
.gr = gm204_gr_new,
.gr = gm200_gr_new,
.sw = gf100_sw_new,
};

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
View File

@ -29,7 +29,7 @@ nvkm-y += nvkm/engine/gr/gk110b.o
nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gk20a.o
nvkm-y += nvkm/engine/gr/gm107.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm200.o
nvkm-y += nvkm/engine/gr/gm206.o
nvkm-y += nvkm/engine/gr/gm20b.o
@ -47,6 +47,6 @@ nvkm-y += nvkm/engine/gr/ctxgk110b.o
nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgk20a.o
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/ctxgm204.o
nvkm-y += nvkm/engine/gr/ctxgm200.o
nvkm-y += nvkm/engine/gr/ctxgm206.o
nvkm-y += nvkm/engine/gr/ctxgm20b.o

26
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View File

@ -97,10 +97,10 @@ void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_pagepool(struct gf100_grctx *);
void gm107_grctx_generate_attrib(struct gf100_grctx *);
extern const struct gf100_grctx_func gm204_grctx;
void gm204_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gm204_grctx_generate_tpcid(struct gf100_gr *);
void gm204_grctx_generate_405b60(struct gf100_gr *);
extern const struct gf100_grctx_func gm200_grctx;
void gm200_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *);
void gm200_grctx_generate_tpcid(struct gf100_gr *);
void gm200_grctx_generate_405b60(struct gf100_gr *);
extern const struct gf100_grctx_func gm206_grctx;
extern const struct gf100_grctx_func gm20b_grctx;
@ -211,18 +211,18 @@ extern const struct gf100_gr_init gk208_grctx_init_crstr_0[];
extern const struct gf100_gr_init gm107_grctx_init_gpc_unk_0[];
extern const struct gf100_gr_init gm107_grctx_init_wwdx_0[];
extern const struct gf100_gr_pack gm204_grctx_pack_icmd[];
extern const struct gf100_gr_pack gm200_grctx_pack_icmd[];
extern const struct gf100_gr_pack gm204_grctx_pack_mthd[];
extern const struct gf100_gr_pack gm200_grctx_pack_mthd[];
extern const struct gf100_gr_pack gm204_grctx_pack_hub[];
extern const struct gf100_gr_pack gm200_grctx_pack_hub[];
extern const struct gf100_gr_init gm204_grctx_init_prop_0[];
extern const struct gf100_gr_init gm204_grctx_init_setup_0[];
extern const struct gf100_gr_init gm204_grctx_init_gpm_0[];
extern const struct gf100_gr_init gm204_grctx_init_gpc_unk_2[];
extern const struct gf100_gr_init gm200_grctx_init_prop_0[];
extern const struct gf100_gr_init gm200_grctx_init_setup_0[];
extern const struct gf100_gr_init gm200_grctx_init_gpm_0[];
extern const struct gf100_gr_init gm200_grctx_init_gpc_unk_2[];
extern const struct gf100_gr_pack gm204_grctx_pack_tpc[];
extern const struct gf100_gr_pack gm200_grctx_pack_tpc[];
extern const struct gf100_gr_pack gm204_grctx_pack_ppc[];
extern const struct gf100_gr_pack gm200_grctx_pack_ppc[];
#endif

118
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c
View File

@ -28,7 +28,7 @@
******************************************************************************/
static const struct gf100_gr_init
gm204_grctx_init_icmd_0[] = {
gm200_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000002 },
{ 0x0006aa, 1, 0x01, 0x00000001 },
{ 0x0006ad, 2, 0x01, 0x00000100 },
@ -295,13 +295,13 @@ gm204_grctx_init_icmd_0[] = {
};
const struct gf100_gr_pack
gm204_grctx_pack_icmd[] = {
{ gm204_grctx_init_icmd_0 },
gm200_grctx_pack_icmd[] = {
{ gm200_grctx_init_icmd_0 },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_b197_0[] = {
gm200_grctx_init_b197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@ -643,14 +643,14 @@ gm204_grctx_init_b197_0[] = {
};
const struct gf100_gr_pack
gm204_grctx_pack_mthd[] = {
{ gm204_grctx_init_b197_0, 0xb197 },
gm200_grctx_pack_mthd[] = {
{ gm200_grctx_init_b197_0, 0xb197 },
{ gf100_grctx_init_902d_0, 0x902d },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_fe_0[] = {
gm200_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
@ -671,7 +671,7 @@ gm204_grctx_init_fe_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_ds_0[] = {
gm200_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x8f8001bf },
{ 0x405830, 1, 0x04, 0x04001000 },
{ 0x405834, 1, 0x04, 0x08000000 },
@ -685,7 +685,7 @@ gm204_grctx_init_ds_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_cwd_0[] = {
gm200_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{ 0x405b20, 1, 0x04, 0x04000000 },
@ -695,7 +695,7 @@ gm204_grctx_init_cwd_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_pd_0[] = {
gm200_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x17410001 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@ -711,7 +711,7 @@ gm204_grctx_init_pd_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_be_0[] = {
gm200_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32882a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@ -724,22 +724,22 @@ gm204_grctx_init_be_0[] = {
};
const struct gf100_gr_pack
gm204_grctx_pack_hub[] = {
gm200_grctx_pack_hub[] = {
{ gf100_grctx_init_main_0 },
{ gm204_grctx_init_fe_0 },
{ gm200_grctx_init_fe_0 },
{ gk110_grctx_init_pri_0 },
{ gk104_grctx_init_memfmt_0 },
{ gm204_grctx_init_ds_0 },
{ gm204_grctx_init_cwd_0 },
{ gm204_grctx_init_pd_0 },
{ gm200_grctx_init_ds_0 },
{ gm200_grctx_init_cwd_0 },
{ gm200_grctx_init_pd_0 },
{ gk208_grctx_init_rstr2d_0 },
{ gk104_grctx_init_scc_0 },
{ gm204_grctx_init_be_0 },
{ gm200_grctx_init_be_0 },
{}
};
const struct gf100_gr_init
gm204_grctx_init_prop_0[] = {
gm200_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38e01e00 },
{ 0x418404, 1, 0x04, 0x70001fff },
{ 0x41840c, 1, 0x04, 0x20001008 },
@ -753,7 +753,7 @@ gm204_grctx_init_prop_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_gpc_unk_1[] = {
gm200_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
@ -765,7 +765,7 @@ gm204_grctx_init_gpc_unk_1[] = {
};
const struct gf100_gr_init
gm204_grctx_init_setup_0[] = {
gm200_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x418810, 1, 0x04, 0x00000000 },
@ -779,7 +779,7 @@ gm204_grctx_init_setup_0[] = {
};
const struct gf100_gr_init
gm204_grctx_init_gpm_0[] = {
gm200_grctx_init_gpm_0[] = {
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
{ 0x418c6c, 1, 0x04, 0x00000001 },
@ -788,7 +788,7 @@ gm204_grctx_init_gpm_0[] = {
};
const struct gf100_gr_init
gm204_grctx_init_gpc_unk_2[] = {
gm200_grctx_init_gpc_unk_2[] = {
{ 0x418e00, 1, 0x04, 0x90040000 },
{ 0x418e24, 1, 0x04, 0x00000000 },
{ 0x418e28, 1, 0x04, 0x00000030 },
@ -800,21 +800,21 @@ gm204_grctx_init_gpc_unk_2[] = {
};
static const struct gf100_gr_pack
gm204_grctx_pack_gpc[] = {
gm200_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
{ gm204_grctx_init_prop_0 },
{ gm204_grctx_init_gpc_unk_1 },
{ gm204_grctx_init_setup_0 },
{ gm200_grctx_init_prop_0 },
{ gm200_grctx_init_gpc_unk_1 },
{ gm200_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gk208_grctx_init_crstr_0 },
{ gm204_grctx_init_gpm_0 },
{ gm204_grctx_init_gpc_unk_2 },
{ gm200_grctx_init_gpm_0 },
{ gm200_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_pe_0[] = {
gm200_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000029 },
{ 0x419888, 1, 0x04, 0x00000000 },
@ -822,7 +822,7 @@ gm204_grctx_init_pe_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_tex_0[] = {
gm200_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000005 },
{ 0x419a08, 1, 0x04, 0x00000621 },
@ -838,7 +838,7 @@ gm204_grctx_init_tex_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_mpc_0[] = {
gm200_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000009a },
{ 0x419c04, 1, 0x04, 0x80000bd6 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@ -853,14 +853,14 @@ gm204_grctx_init_mpc_0[] = {
};
static const struct gf100_gr_init
gm204_grctx_init_l1c_0[] = {
gm200_grctx_init_l1c_0[] = {
{ 0x419c84, 1, 0x04, 0x0000003e },
{ 0x419c90, 1, 0x04, 0x0000000a },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_sm_0[] = {
gm200_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
{ 0x419e44, 1, 0x04, 0x00d3eff2 },
@ -881,23 +881,23 @@ gm204_grctx_init_sm_0[] = {
};
const struct gf100_gr_pack
gm204_grctx_pack_tpc[] = {
{ gm204_grctx_init_pe_0 },
{ gm204_grctx_init_tex_0 },
{ gm204_grctx_init_mpc_0 },
{ gm204_grctx_init_l1c_0 },
{ gm204_grctx_init_sm_0 },
gm200_grctx_pack_tpc[] = {
{ gm200_grctx_init_pe_0 },
{ gm200_grctx_init_tex_0 },
{ gm200_grctx_init_mpc_0 },
{ gm200_grctx_init_l1c_0 },
{ gm200_grctx_init_sm_0 },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_pes_0[] = {
gm200_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x0000000e },
{}
};
static const struct gf100_gr_init
gm204_grctx_init_cbm_0[] = {
gm200_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x00000000 },
{ 0x41bec4, 1, 0x04, 0x01030000 },
{ 0x41bee4, 1, 0x04, 0x00000000 },
@ -907,9 +907,9 @@ gm204_grctx_init_cbm_0[] = {
};
const struct gf100_gr_pack
gm204_grctx_pack_ppc[] = {
{ gm204_grctx_init_pes_0 },
{ gm204_grctx_init_cbm_0 },
gm200_grctx_pack_ppc[] = {
{ gm200_grctx_init_pes_0 },
{ gm200_grctx_init_cbm_0 },
{ gm107_grctx_init_wwdx_0 },
{}
};
@ -919,7 +919,7 @@ gm204_grctx_pack_ppc[] = {
******************************************************************************/
void
gm204_grctx_generate_tpcid(struct gf100_gr *gr)
gm200_grctx_generate_tpcid(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
int gpc, tpc, id;
@ -937,7 +937,7 @@ gm204_grctx_generate_tpcid(struct gf100_gr *gr)
}
static void
gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
gm200_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 fbp_count = nvkm_rd32(device, 0x12006c);
@ -946,7 +946,7 @@ gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr)
}
void
gm204_grctx_generate_405b60(struct gf100_gr *gr)
gm200_grctx_generate_405b60(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
@ -978,7 +978,7 @@ gm204_grctx_generate_405b60(struct gf100_gr *gr)
}
void
gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const struct gf100_grctx_func *grctx = gr->func->grctx;
@ -998,7 +998,7 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
grctx->attrib(info);
grctx->unkn(gr);
gm204_grctx_generate_tpcid(gr);
gm200_grctx_generate_tpcid(gr);
gf100_grctx_generate_r406028(gr);
gk104_grctx_generate_r418bb8(gr);
@ -1008,13 +1008,13 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
gm204_grctx_generate_rop_active_fbps(gr);
gm200_grctx_generate_rop_active_fbps(gr);
for (tmp = 0, i = 0; i < gr->gpc_nr; i++)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nvkm_wr32(device, 0x4041c4, tmp);
gm204_grctx_generate_405b60(gr);
gm200_grctx_generate_405b60(gr);
gf100_gr_icmd(gr, grctx->icmd);
nvkm_wr32(device, 0x404154, 0x00000800);
@ -1025,16 +1025,16 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
}
const struct gf100_grctx_func
gm204_grctx = {
.main = gm204_grctx_generate_main,
gm200_grctx = {
.main = gm200_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gm204_grctx_pack_hub,
.gpc = gm204_grctx_pack_gpc,
.hub = gm200_grctx_pack_hub,
.gpc = gm200_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gm204_grctx_pack_tpc,
.ppc = gm204_grctx_pack_ppc,
.icmd = gm204_grctx_pack_icmd,
.mthd = gm204_grctx_pack_mthd,
.tpc = gm200_grctx_pack_tpc,
.ppc = gm200_grctx_pack_ppc,
.icmd = gm200_grctx_pack_icmd,
.mthd = gm200_grctx_pack_mthd,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,

20
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c
View File

@ -38,28 +38,28 @@ gm206_grctx_init_gpc_unk_1[] = {
static const struct gf100_gr_pack
gm206_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
{ gm204_grctx_init_prop_0 },
{ gm200_grctx_init_prop_0 },
{ gm206_grctx_init_gpc_unk_1 },
{ gm204_grctx_init_setup_0 },
{ gm200_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gk208_grctx_init_crstr_0 },
{ gm204_grctx_init_gpm_0 },
{ gm204_grctx_init_gpc_unk_2 },
{ gm200_grctx_init_gpm_0 },
{ gm200_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
const struct gf100_grctx_func
gm206_grctx = {
.main = gm204_grctx_generate_main,
.main = gm200_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gm204_grctx_pack_hub,
.hub = gm200_grctx_pack_hub,
.gpc = gm206_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gm204_grctx_pack_tpc,
.ppc = gm204_grctx_pack_ppc,
.icmd = gm204_grctx_pack_icmd,
.mthd = gm204_grctx_pack_mthd,
.tpc = gm200_grctx_pack_tpc,
.ppc = gm200_grctx_pack_ppc,
.icmd = gm200_grctx_pack_icmd,
.mthd = gm200_grctx_pack_mthd,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c
View File

@ -54,7 +54,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
grctx->unkn(gr);
gm204_grctx_generate_tpcid(gr);
gm200_grctx_generate_tpcid(gr);
gm20b_grctx_generate_r406028(gr);
gk104_grctx_generate_r418bb8(gr);
@ -70,7 +70,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4);
nvkm_wr32(device, 0x4041c4, tmp);
gm204_grctx_generate_405b60(gr);
gm200_grctx_generate_405b60(gr);
gf100_gr_wait_idle(gr);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -143,7 +143,7 @@ int gk20a_gr_new_(const struct gf100_gr_func *, struct nvkm_device *,
void gk20a_gr_dtor(struct gf100_gr *);
int gk20a_gr_init(struct gf100_gr *);
int gm204_gr_init(struct gf100_gr *);
int gm200_gr_init(struct gf100_gr *);
#define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object)
@ -280,5 +280,5 @@ extern const struct gf100_gr_init gm107_gr_init_wwdx_0[];
extern const struct gf100_gr_init gm107_gr_init_cbm_0[];
void gm107_gr_init_bios(struct gf100_gr *);
extern const struct gf100_gr_pack gm204_gr_pack_mmio[];
extern const struct gf100_gr_pack gm200_gr_pack_mmio[];
#endif

72
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c → drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -31,7 +31,7 @@
******************************************************************************/
static const struct gf100_gr_init
gm204_gr_init_main_0[] = {
gm200_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003003e2 },
{ 0x400088, 1, 0x04, 0xe007bfe7 },
{ 0x40008c, 1, 0x04, 0x00060000 },
@ -47,7 +47,7 @@ gm204_gr_init_main_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_fe_0[] = {
gm200_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{ 0x4041b4, 1, 0x04, 0x00000000 },
@ -56,7 +56,7 @@ gm204_gr_init_fe_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_ds_0[] = {
gm200_gr_init_ds_0[] = {
{ 0x40583c, 1, 0x04, 0x00000000 },
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x40584c, 1, 0x04, 0x00000001 },
@ -67,7 +67,7 @@ gm204_gr_init_ds_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_sked_0[] = {
gm200_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440434 },
{ 0x407048, 1, 0x04, 0x00000008 },
@ -75,7 +75,7 @@ gm204_gr_init_sked_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_tpccs_0[] = {
gm200_gr_init_tpccs_0[] = {
{ 0x419d60, 1, 0x04, 0x0000003f },
{ 0x419d88, 3, 0x04, 0x00000000 },
{ 0x419dc4, 1, 0x04, 0x00000000 },
@ -95,7 +95,7 @@ gm204_gr_init_tpccs_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_pe_0[] = {
gm200_gr_init_pe_0[] = {
{ 0x419900, 1, 0x04, 0x000000ff },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x41980c, 1, 0x04, 0x00000010 },
@ -108,7 +108,7 @@ gm204_gr_init_pe_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_sm_0[] = {
gm200_gr_init_sm_0[] = {
{ 0x419e30, 1, 0x04, 0x000000ff },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
@ -125,20 +125,20 @@ gm204_gr_init_sm_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_l1c_1[] = {
gm200_gr_init_l1c_1[] = {
{ 0x419cf8, 2, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm204_gr_init_sm_1[] = {
gm200_gr_init_sm_1[] = {
{ 0x419f74, 1, 0x04, 0x00055155 },
{ 0x419f80, 4, 0x04, 0x00000000 },
{}
};
static const struct gf100_gr_init
gm204_gr_init_l1c_2[] = {
gm200_gr_init_l1c_2[] = {
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x3f006022 },
{ 0x419c88, 1, 0x04, 0x00210000 },
@ -146,7 +146,7 @@ gm204_gr_init_l1c_2[] = {
};
static const struct gf100_gr_init
gm204_gr_init_pes_0[] = {
gm200_gr_init_pes_0[] = {
{ 0x41be50, 1, 0x04, 0x000000ff },
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
@ -158,7 +158,7 @@ gm204_gr_init_pes_0[] = {
};
static const struct gf100_gr_init
gm204_gr_init_be_0[] = {
gm200_gr_init_be_0[] = {
{ 0x408890, 1, 0x04, 0x000000ff },
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
@ -184,15 +184,15 @@ gm204_gr_init_be_0[] = {
};
const struct gf100_gr_pack
gm204_gr_pack_mmio[] = {
{ gm204_gr_init_main_0 },
{ gm204_gr_init_fe_0 },
gm200_gr_pack_mmio[] = {
{ gm200_gr_init_main_0 },
{ gm200_gr_init_fe_0 },
{ gf100_gr_init_pri_0 },
{ gf100_gr_init_rstr2d_0 },
{ gf100_gr_init_pd_0 },
{ gm204_gr_init_ds_0 },
{ gm200_gr_init_ds_0 },
{ gm107_gr_init_scc_0 },
{ gm204_gr_init_sked_0 },
{ gm200_gr_init_sked_0 },
{ gk110_gr_init_cwd_0 },
{ gm107_gr_init_prop_0 },
{ gk208_gr_init_gpc_unk_0 },
@ -203,25 +203,25 @@ gm204_gr_pack_mmio[] = {
{ gf100_gr_init_gpm_0 },
{ gm107_gr_init_gpc_unk_1 },
{ gf100_gr_init_gcc_0 },
{ gm204_gr_init_tpccs_0 },
{ gm200_gr_init_tpccs_0 },
{ gm107_gr_init_tex_0 },
{ gm204_gr_init_pe_0 },
{ gm200_gr_init_pe_0 },
{ gm107_gr_init_l1c_0 },
{ gf100_gr_init_mpc_0 },
{ gm204_gr_init_sm_0 },
{ gm204_gr_init_l1c_1 },
{ gm204_gr_init_sm_1 },
{ gm204_gr_init_l1c_2 },
{ gm204_gr_init_pes_0 },
{ gm200_gr_init_sm_0 },
{ gm200_gr_init_l1c_1 },
{ gm200_gr_init_sm_1 },
{ gm200_gr_init_l1c_2 },
{ gm200_gr_init_pes_0 },
{ gm107_gr_init_wwdx_0 },
{ gm107_gr_init_cbm_0 },
{ gm204_gr_init_be_0 },
{ gm200_gr_init_be_0 },
{}
};
const struct gf100_gr_pack *
gm204_gr_data[] = {
gm204_gr_pack_mmio,
gm200_gr_data[] = {
gm200_gr_pack_mmio,
NULL
};
@ -230,13 +230,13 @@ gm204_gr_data[] = {
******************************************************************************/
static int
gm204_gr_init_ctxctl(struct gf100_gr *gr)
gm200_gr_init_ctxctl(struct gf100_gr *gr)
{
return 0;
}
int
gm204_gr_init(struct gf100_gr *gr)
gm200_gr_init(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
@ -348,15 +348,15 @@ gm204_gr_init(struct gf100_gr *gr)
gf100_gr_zbc_init(gr);
return gm204_gr_init_ctxctl(gr);
return gm200_gr_init_ctxctl(gr);
}
static const struct gf100_gr_func
gm204_gr = {
.init = gm204_gr_init,
.mmio = gm204_gr_pack_mmio,
gm200_gr = {
.init = gm200_gr_init,
.mmio = gm200_gr_pack_mmio,
.ppc_nr = 2,
.grctx = &gm204_grctx,
.grctx = &gm200_grctx,
.sclass = {
{ -1, -1, FERMI_TWOD_A },
{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
@ -367,7 +367,7 @@ gm204_gr = {
};
int
gm204_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
{
return gf100_gr_new_(&gm204_gr, device, index, pgr);
return gf100_gr_new_(&gm200_gr, device, index, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c
View File

@ -28,8 +28,8 @@
static const struct gf100_gr_func
gm206_gr = {
.init = gm204_gr_init,
.mmio = gm204_gr_pack_mmio,
.init = gm200_gr_init,
.mmio = gm200_gr_pack_mmio,
.ppc_nr = 2,
.grctx = &gm206_grctx,
.sclass = {