Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "All fairly small: radeon stability and a panic path fix. Mostly radeon fixes, suspend/resume fix, stability on the CIK chipsets, along with a locking check avoidance patch for panic times regression" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: use the CP DMA on CIK drm/radeon: sync page table updates drm/radeon: fix vm buffer size estimation drm/crtc-helper: skip locking checks in panicking path drm/radeon/dpm: resume fixes for some systems
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commit
9e9a928eed
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@ -29,6 +29,7 @@
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/moduleparam.h>
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@ -88,7 +89,13 @@ bool drm_helper_encoder_in_use(struct drm_encoder *encoder)
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struct drm_connector *connector;
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struct drm_device *dev = encoder->dev;
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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/*
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* We can expect this mutex to be locked if we are not panicking.
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* Locking is currently fubar in the panic handler.
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*/
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if (!oops_in_progress)
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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if (connector->encoder == encoder)
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return true;
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@ -112,7 +119,13 @@ bool drm_helper_crtc_in_use(struct drm_crtc *crtc)
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struct drm_encoder *encoder;
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struct drm_device *dev = crtc->dev;
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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/*
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* We can expect this mutex to be locked if we are not panicking.
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* Locking is currently fubar in the panic handler.
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*/
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if (!oops_in_progress)
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WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
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if (encoder->crtc == crtc && drm_helper_encoder_in_use(encoder))
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return true;
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@ -270,8 +270,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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radeon_crtc->enabled = true;
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/* adjust pm to dpms changes BEFORE enabling crtcs */
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radeon_pm_compute_clocks(rdev);
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atombios_enable_crtc(crtc, ATOM_ENABLE);
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if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
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atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
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@ -289,10 +287,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
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atombios_enable_crtc(crtc, ATOM_DISABLE);
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radeon_crtc->enabled = false;
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/* adjust pm to dpms changes AFTER disabling crtcs */
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radeon_pm_compute_clocks(rdev);
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break;
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}
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/* adjust pm to dpms */
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radeon_pm_compute_clocks(rdev);
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}
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static void
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@ -2049,8 +2049,8 @@ static struct radeon_asic ci_asic = {
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.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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.dma = &cik_copy_dma,
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.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = &cik_copy_dma,
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.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
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.copy = &cik_copy_cpdma,
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.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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},
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.surface = {
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.set_reg = r600_set_surface_reg,
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@ -1558,6 +1558,10 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
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drm_kms_helper_poll_enable(dev);
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/* set the power state here in case we are a PX system or headless */
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if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
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radeon_pm_compute_clocks(rdev);
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if (fbcon) {
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radeon_fbdev_set_suspend(rdev, 0);
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console_unlock();
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@ -1104,7 +1104,6 @@ static void radeon_pm_resume_dpm(struct radeon_device *rdev)
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if (ret)
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goto dpm_resume_fail;
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rdev->pm.dpm_enabled = true;
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radeon_pm_compute_clocks(rdev);
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return;
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dpm_resume_fail:
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@ -132,7 +132,7 @@ struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
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struct radeon_cs_reloc *list;
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unsigned i, idx;
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list = kmalloc_array(vm->max_pde_used + 1,
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list = kmalloc_array(vm->max_pde_used + 2,
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sizeof(struct radeon_cs_reloc), GFP_KERNEL);
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if (!list)
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return NULL;
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@ -585,7 +585,8 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
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{
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static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
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uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
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struct radeon_bo *pd = vm->page_directory;
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uint64_t pd_addr = radeon_bo_gpu_offset(pd);
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uint64_t last_pde = ~0, last_pt = ~0;
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unsigned count = 0, pt_idx, ndw;
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struct radeon_ib ib;
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@ -642,6 +643,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev,
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incr, R600_PTE_VALID);
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if (ib.length_dw != 0) {
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radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj);
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radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use);
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r = radeon_ib_schedule(rdev, &ib, NULL);
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if (r) {
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@ -689,15 +691,18 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
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/* walk over the address space and update the page tables */
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for (addr = start; addr < end; ) {
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uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE;
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struct radeon_bo *pt = vm->page_tables[pt_idx].bo;
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unsigned nptes;
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uint64_t pte;
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radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj);
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if ((addr & ~mask) == (end & ~mask))
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nptes = end - addr;
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else
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nptes = RADEON_VM_PTE_COUNT - (addr & mask);
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pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo);
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pte = radeon_bo_gpu_offset(pt);
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pte += (addr & mask) * 8;
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if ((last_pte + 8 * count) != pte) {
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