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- Add support for AST2400 and AST2600 hw to aspeed_edac (Troy Lee) 

- Remove an orphaned mv64x60_edac driver. Good riddance. (Michael Ellerman)
 
 - Add a new igen6 driver for Intel client SoCs with an integrated memory
 controller and using in-band ECC (Qiuxu Zhuo and Tony Luck)
 
 - The usual smattering of fixes and cleanups all over.
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Merge tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:
 "Somewhat busier than usual this cycle:

   - Add support for AST2400 and AST2600 hw to aspeed_edac (Troy Lee)

   - Remove an orphaned mv64x60_edac driver. Good riddance (Michael
     Ellerman)

   - Add a new igen6 driver for Intel client SoCs with an integrated
     memory controller and using in-band ECC (Qiuxu Zhuo and Tony Luck)

   - The usual smattering of fixes and cleanups all over"

* tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/mv64x60: Remove orphan mv64x60 driver
  EDAC/aspeed: Add support for AST2400 and AST2600
  ARM: dts: aspeed: Add AST2600 EDAC into common devicetree
  dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
  EDAC/amd64: Fix PCI component registration
  EDAC/igen6: ecclog_llist can be static
  EDAC/i10nm: Add Intel Sapphire Rapids server support
  EDAC: Add DDR5 new memory type
  EDAC/i10nm: Use readl() to access MMIO registers
  MAINTAINERS: Add entry for Intel IGEN6 EDAC driver
  EDAC/igen6: Add debugfs interface for Intel client SoC EDAC driver
  EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC
  EDAC/synopsys: Return the correct value in mc_probe()
  MAINTAINERS: Clean up the F: entries for some EDAC drivers
  EDAC: Add three new memory types
  EDAC: Fix some kernel-doc markups
  EDAC: Do not issue useless debug statements in the polling routine
  EDAC/amd64: Remove unneeded breaks
This commit is contained in:
Linus Torvalds 2020-12-14 12:55:35 -08:00
parent 9e4b0d55d8 f84b799996
commit 9e7f25886b
32 changed files with 1119 additions and 1080 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
View File

@ -1,6 +1,6 @@
Aspeed AST2500 SoC EDAC node
Aspeed BMC SoC EDAC node
The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
correction check).
The memory controller supports SECDED (single bit error correction, double bit
@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.
Required properties:
- compatible: should be "aspeed,ast2500-sdram-edac"
- compatible: should be one of
- "aspeed,ast2400-sdram-edac"
- "aspeed,ast2500-sdram-edac"
- "aspeed,ast2600-sdram-edac"
- reg: sdram controller register set should be <0x1e6e0000 0x174>
- interrupts: should be AVIC interrupt #0

11
MAINTAINERS
View File

@ -2485,7 +2485,7 @@ F: drivers/clk/socfpga/
ARM/SOCFPGA EDAC SUPPORT
M: Dinh Nguyen <dinguyen@kernel.org>
S: Maintained
F: drivers/edac/altera_edac.
F: drivers/edac/altera_edac.[ch]
ARM/SPREADTRUM SoC SUPPORT
M: Orson Zhai <orsonzhai@gmail.com>
@ -6370,6 +6370,13 @@ L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/ie31200_edac.c
EDAC-IGEN6
M: Tony Luck <tony.luck@intel.com>
R: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/igen6_edac.c
EDAC-MPC85XX
M: Johannes Thumshirn <morbidrsa@gmail.com>
L: linux-edac@vger.kernel.org
@ -6419,7 +6426,7 @@ EDAC-SKYLAKE
M: Tony Luck <tony.luck@intel.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/skx_*.c
F: drivers/edac/skx_*.[ch]
EDAC-TI
M: Tero Kristo <t-kristo@ti.com>

6
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -69,6 +69,12 @@
always-on;
};
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac", "syscon";
reg = <0x1e6e0000 0x174>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;

22
drivers/edac/Kconfig
View File

@ -269,6 +269,15 @@ config EDAC_PND2
first used on the Apollo Lake platform and Denverton
micro-server but may appear on others in the future.
config EDAC_IGEN6
tristate "Intel client SoC Integrated MC"
depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
help
Support for error detection and correction on the Intel
client SoC Integrated Memory Controller using In-Band ECC IP.
This In-Band ECC is first used on the Elkhart Lake SoC but
may appear on others in the future.
config EDAC_MPC85XX
bool "Freescale MPC83xx / MPC85xx"
depends on FSL_SOC && EDAC=y
@ -283,13 +292,6 @@ config EDAC_LAYERSCAPE
Support for error detection and correction on Freescale memory
controllers on Layerscape SoCs.
config EDAC_MV64X60
tristate "Marvell MV64x60"
depends on MV64X60
help
Support for error detection and correction on the Marvell
MV64360 and MV64460 chipsets.
config EDAC_PASEMI
tristate "PA Semi PWRficient"
depends on PPC_PASEMI && PCI
@ -515,10 +517,10 @@ config EDAC_QCOM
health, you should probably say 'Y' here.
config EDAC_ASPEED
tristate "Aspeed AST 2500 SoC"
depends on MACH_ASPEED_G5
tristate "Aspeed AST BMC SoC"
depends on ARCH_ASPEED
help
Support for error detection and correction on the Aspeed AST 2500 SoC.
Support for error detection and correction on the Aspeed AST BMC SoC.
First, ECC must be configured in the bootloader. Then, this driver
will expose error counters via the EDAC kernel framework.

2
drivers/edac/Makefile
View File

@ -32,6 +32,7 @@ obj-$(CONFIG_EDAC_I7300) += i7300_edac.o
obj-$(CONFIG_EDAC_I7CORE) += i7core_edac.o
obj-$(CONFIG_EDAC_SBRIDGE) += sb_edac.o
obj-$(CONFIG_EDAC_PND2) += pnd2_edac.o
obj-$(CONFIG_EDAC_IGEN6) += igen6_edac.o
obj-$(CONFIG_EDAC_E7XXX) += e7xxx_edac.o
obj-$(CONFIG_EDAC_E752X) += e752x_edac.o
obj-$(CONFIG_EDAC_I82443BXGX) += i82443bxgx_edac.o
@ -64,7 +65,6 @@ obj-$(CONFIG_EDAC_SKX) += skx_edac.o
i10nm_edac-y := skx_common.o i10nm_base.o
obj-$(CONFIG_EDAC_I10NM) += i10nm_edac.o
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
obj-$(CONFIG_EDAC_AMD8111) += amd8111_edac.o

34
drivers/edac/amd64_edac.c
View File

@ -18,6 +18,9 @@ static struct amd64_family_type *fam_type;
/* Per-node stuff */
static struct ecc_settings **ecc_stngs;
/* Device for the PCI component */
static struct device *pci_ctl_dev;
/*
* Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
* bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
@ -2461,14 +2464,11 @@ static int map_err_sym_to_channel(int err_sym, int sym_size)
case 0x20:
case 0x21:
return 0;
break;
case 0x22:
case 0x23:
return 1;
break;
default:
return err_sym >> 4;
break;
}
/* x8 symbols */
else
@ -2478,17 +2478,12 @@ static int map_err_sym_to_channel(int err_sym, int sym_size)
WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
err_sym);
return -1;
break;
case 0x11:
return 0;
break;
case 0x12:
return 1;
break;
default:
return err_sym >> 3;
break;
}
return -1;
}
@ -2683,6 +2678,9 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
return -ENODEV;
}
if (!pci_ctl_dev)
pci_ctl_dev = &pvt->F0->dev;
edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));
@ -2707,6 +2705,9 @@ reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
return -ENODEV;
}
if (!pci_ctl_dev)
pci_ctl_dev = &pvt->F2->dev;
edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
@ -3623,21 +3624,10 @@ static void remove_one_instance(unsigned int nid)
static void setup_pci_device(void)
{
struct mem_ctl_info *mci;
struct amd64_pvt *pvt;
if (pci_ctl)
return;
mci = edac_mc_find(0);
if (!mci)
return;
pvt = mci->pvt_info;
if (pvt->umc)
pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR);
else
pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
pci_ctl = edac_pci_create_generic_ctl(pci_ctl_dev, EDAC_MOD_STR);
if (!pci_ctl) {
pr_warn("%s(): Unable to create PCI control\n", __func__);
pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
@ -3716,6 +3706,8 @@ static int __init amd64_edac_init(void)
return 0;
err_pci:
pci_ctl_dev = NULL;
msrs_free(msrs);
msrs = NULL;
@ -3745,6 +3737,8 @@ static void __exit amd64_edac_exit(void)
kfree(ecc_stngs);
ecc_stngs = NULL;
pci_ctl_dev = NULL;
msrs_free(msrs);
msrs = NULL;
}

1
drivers/edac/amd76x_edac.c
View File

@ -179,7 +179,6 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
static void amd76x_check(struct mem_ctl_info *mci)
{
struct amd76x_error_info info;
edac_dbg(3, "\n");
amd76x_get_error_info(mci, &info);
amd76x_process_error_info(mci, &info, 1);
}

7
drivers/edac/aspeed_edac.c
View File

@ -239,7 +239,7 @@ static int init_csrows(struct mem_ctl_info *mci)
int rc;
/* retrieve info about physical memory from device tree */
np = of_find_node_by_path("/memory");
np = of_find_node_by_name(NULL, "memory");
if (!np) {
dev_err(mci->pdev, "dt: missing /memory node\n");
return -ENODEV;
@ -375,10 +375,13 @@ static int aspeed_remove(struct platform_device *pdev)
static const struct of_device_id aspeed_of_match[] = {
{ .compatible = "aspeed,ast2400-sdram-edac" },
{ .compatible = "aspeed,ast2500-sdram-edac" },
{ .compatible = "aspeed,ast2600-sdram-edac" },
{},
};
MODULE_DEVICE_TABLE(of, aspeed_of_match);
static struct platform_driver aspeed_driver = {
.driver = {
@ -392,5 +395,5 @@ module_platform_driver(aspeed_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Stefan Schaeckeler <sschaeck@cisco.com>");
MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver");
MODULE_VERSION("1.0");

1
drivers/edac/e752x_edac.c
View File

@ -980,7 +980,6 @@ static void e752x_check(struct mem_ctl_info *mci)
{
struct e752x_error_info info;
edac_dbg(3, "\n");
e752x_get_error_info(mci, &info);
e752x_process_error_info(mci, &info, 1);
}

1
drivers/edac/e7xxx_edac.c
View File

@ -333,7 +333,6 @@ static void e7xxx_check(struct mem_ctl_info *mci)
{
struct e7xxx_error_info info;
edac_dbg(3, "\n");
e7xxx_get_error_info(mci, &info);
e7xxx_process_error_info(mci, &info, 1);
}

11
drivers/edac/edac_device.h
View File

@ -258,7 +258,7 @@ extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
/**
* edac_device_add_device: Insert the 'edac_dev' structure into the
* edac_device_add_device - Insert the 'edac_dev' structure into the
* edac_device global list and create sysfs entries associated with
* edac_device structure.
*
@ -271,9 +271,8 @@ extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
/**
* edac_device_del_device:
* Remove sysfs entries for specified edac_device structure and
* then remove edac_device structure from global list
* edac_device_del_device - Remove sysfs entries for specified edac_device
* structure and then remove edac_device structure from global list
*
* @dev:
* Pointer to struct &device representing the edac device
@ -286,7 +285,7 @@ extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
/**
* Log correctable errors.
* edac_device_handle_ce_count - Log correctable errors.
*
* @edac_dev: pointer to struct &edac_device_ctl_info
* @inst_nr: number of the instance where the CE error happened
@ -299,7 +298,7 @@ void edac_device_handle_ce_count(struct edac_device_ctl_info *edac_dev,
const char *msg);
/**
* Log uncorrectable errors.
* edac_device_handle_ue_count - Log uncorrectable errors.
*
* @edac_dev: pointer to struct &edac_device_ctl_info
* @inst_nr: number of the instance where the CE error happened

4
drivers/edac/edac_mc.c
View File

@ -158,10 +158,14 @@ const char * const edac_mem_types[] = {
[MEM_DDR3] = "Unbuffered-DDR3",
[MEM_RDDR3] = "Registered-DDR3",
[MEM_LRDDR3] = "Load-Reduced-DDR3-RAM",
[MEM_LPDDR3] = "Low-Power-DDR3-RAM",
[MEM_DDR4] = "Unbuffered-DDR4",
[MEM_RDDR4] = "Registered-DDR4",
[MEM_LPDDR4] = "Low-Power-DDR4-RAM",
[MEM_LRDDR4] = "Load-Reduced-DDR4-RAM",
[MEM_DDR5] = "Unbuffered-DDR5",
[MEM_NVDIMM] = "Non-volatile-RAM",
[MEM_WIO2] = "Wide-IO-2",
};
EXPORT_SYMBOL_GPL(edac_mem_types);

37
drivers/edac/i10nm_base.c
View File

@ -6,13 +6,14 @@
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include <asm/mce.h>
#include "edac_module.h"
#include "skx_common.h"
#define I10NM_REVISION "v0.0.3"
#define I10NM_REVISION "v0.0.4"
#define EDAC_MOD_STR "i10nm_edac"
/* Debug macros */
@ -24,9 +25,13 @@
#define I10NM_GET_IMC_BAR(d, i, reg) \
pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
#define I10NM_GET_DIMMMTR(m, i, j) \
(*(u32 *)((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4))
readl((m)->mbase + 0x2080c + (i) * (m)->chan_mmio_sz + (j) * 4)
#define I10NM_GET_MCDDRTCFG(m, i, j) \
(*(u32 *)((m)->mbase + 0x20970 + (i) * 0x4000 + (j) * 4))
readl((m)->mbase + 0x20970 + (i) * (m)->chan_mmio_sz + (j) * 4)
#define I10NM_GET_MCMTR(m, i) \
readl((m)->mbase + 0x20ef8 + (i) * (m)->chan_mmio_sz)
#define I10NM_GET_AMAP(m, i) \
readl((m)->mbase + 0x20814 + (i) * (m)->chan_mmio_sz)
#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
@ -126,12 +131,22 @@ static struct res_config i10nm_cfg0 = {
.type = I10NM,
.decs_did = 0x3452,
.busno_cfg_offset = 0xcc,
.ddr_chan_mmio_sz = 0x4000,
};
static struct res_config i10nm_cfg1 = {
.type = I10NM,
.decs_did = 0x3452,
.busno_cfg_offset = 0xd0,
.ddr_chan_mmio_sz = 0x4000,
};
static struct res_config spr_cfg = {
.type = SPR,
.decs_did = 0x3252,
.busno_cfg_offset = 0xd0,
.ddr_chan_mmio_sz = 0x8000,
.support_ddr5 = true,
};
static const struct x86_cpu_id i10nm_cpuids[] = {
@ -140,6 +155,7 @@ static const struct x86_cpu_id i10nm_cpuids[] = {
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
{}
};
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
@ -148,18 +164,19 @@ static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
{
u32 mcmtr;
mcmtr = *(u32 *)(imc->mbase + 0x20ef8 + chan * 0x4000);
mcmtr = I10NM_GET_MCMTR(imc, chan);
edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
return !!GET_BITFIELD(mcmtr, 2, 2);
}
static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
struct res_config *cfg)
{
struct skx_pvt *pvt = mci->pvt_info;
struct skx_imc *imc = pvt->imc;
u32 mtr, amap, mcddrtcfg;
struct dimm_info *dimm;
u32 mtr, mcddrtcfg;
int i, j, ndimms;
for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
@ -167,6 +184,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
continue;
ndimms = 0;
amap = I10NM_GET_AMAP(imc, i);
for (j = 0; j < I10NM_NUM_DIMMS; j++) {
dimm = edac_get_dimm(mci, i, j, 0);
mtr = I10NM_GET_DIMMMTR(imc, i, j);
@ -175,8 +193,8 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
mtr, mcddrtcfg, imc->mc, i, j);
if (IS_DIMM_PRESENT(mtr))
ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
imc, i, j);
ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
imc, i, j, cfg);
else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
EDAC_MOD_STR);
@ -300,10 +318,11 @@ static int __init i10nm_init(void)
d->imc[i].lmc = i;
d->imc[i].src_id = src_id;
d->imc[i].node_id = node_id;
d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
"Intel_10nm Socket", EDAC_MOD_STR,
i10nm_get_dimm_config);
i10nm_get_dimm_config, cfg);
if (rc < 0)
goto fail;
}

1
drivers/edac/i3000_edac.c
View File

@ -273,7 +273,6 @@ static void i3000_check(struct mem_ctl_info *mci)
{
struct i3000_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i3000_get_error_info(mci, &info);
i3000_process_error_info(mci, &info, 1);
}

1
drivers/edac/i3200_edac.c
View File

@ -253,7 +253,6 @@ static void i3200_check(struct mem_ctl_info *mci)
{
struct i3200_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i3200_get_and_clear_error_info(mci, &info);
i3200_process_error_info(mci, &info);
}

2
drivers/edac/i5000_edac.c
View File

@ -765,7 +765,7 @@ static void i5000_clear_error(struct mem_ctl_info *mci)
static void i5000_check_error(struct mem_ctl_info *mci)
{
struct i5000_error_info info;
edac_dbg(4, "MC%d\n", mci->mc_idx);
i5000_get_error_info(mci, &info);
i5000_process_error_info(mci, &info, 1);
}

2
drivers/edac/i5400_edac.c
View File

@ -686,7 +686,7 @@ static void i5400_clear_error(struct mem_ctl_info *mci)
static void i5400_check_error(struct mem_ctl_info *mci)
{
struct i5400_error_info info;
edac_dbg(4, "MC%d\n", mci->mc_idx);
i5400_get_error_info(mci, &info);
i5400_process_error_info(mci, &info);
}

1
drivers/edac/i82443bxgx_edac.c
View File

@ -176,7 +176,6 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
{
struct i82443bxgx_edacmc_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i82443bxgx_edacmc_get_error_info(mci, &info);
i82443bxgx_edacmc_process_error_info(mci, &info, 1);
}

1
drivers/edac/i82860_edac.c
View File

@ -135,7 +135,6 @@ static void i82860_check(struct mem_ctl_info *mci)
{
struct i82860_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i82860_get_error_info(mci, &info);
i82860_process_error_info(mci, &info, 1);
}

1
drivers/edac/i82875p_edac.c
View File

@ -262,7 +262,6 @@ static void i82875p_check(struct mem_ctl_info *mci)
{
struct i82875p_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i82875p_get_error_info(mci, &info);
i82875p_process_error_info(mci, &info, 1);
}

1
drivers/edac/i82975x_edac.c
View File

@ -330,7 +330,6 @@ static void i82975x_check(struct mem_ctl_info *mci)
{
struct i82975x_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
i82975x_get_error_info(mci, &info);
i82975x_process_error_info(mci, &info, 1);
}

1
drivers/edac/ie31200_edac.c
View File

@ -333,7 +333,6 @@ static void ie31200_check(struct mem_ctl_info *mci)
{
struct ie31200_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
ie31200_get_and_clear_error_info(mci, &info);
ie31200_process_error_info(mci, &info);
}

977
drivers/edac/igen6_edac.c Normal file
View File

@ -0,0 +1,977 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Intel client SoC with integrated memory controller using IBECC
*
* Copyright (C) 2020 Intel Corporation
*
* The In-Band ECC (IBECC) IP provides ECC protection to all or specific
* regions of the physical memory space. It's used for memory controllers
* that don't support the out-of-band ECC which often needs an additional
* storage device to each channel for storing ECC data.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/irq_work.h>
#include <linux/llist.h>
#include <linux/genalloc.h>
#include <linux/edac.h>
#include <linux/bits.h>
#include <linux/io.h>
#include <asm/mach_traps.h>
#include <asm/nmi.h>
#include "edac_mc.h"
#include "edac_module.h"
#define IGEN6_REVISION "v2.4"
#define EDAC_MOD_STR "igen6_edac"
#define IGEN6_NMI_NAME "igen6_ibecc"
/* Debug macros */
#define igen6_printk(level, fmt, arg...) \
edac_printk(level, "igen6", fmt, ##arg)
#define igen6_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level, "igen6", fmt, ##arg)
#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
#define NUM_IMC 1 /* Max memory controllers */
#define NUM_CHANNELS 2 /* Max channels */
#define NUM_DIMMS 2 /* Max DIMMs per channel */
#define _4GB BIT_ULL(32)
/* Size of physical memory */
#define TOM_OFFSET 0xa0
/* Top of low usable DRAM */
#define TOLUD_OFFSET 0xbc
/* Capability register C */
#define CAPID_C_OFFSET 0xec
#define CAPID_C_IBECC BIT(15)
/* Error Status */
#define ERRSTS_OFFSET 0xc8
#define ERRSTS_CE BIT_ULL(6)
#define ERRSTS_UE BIT_ULL(7)
/* Error Command */
#define ERRCMD_OFFSET 0xca
#define ERRCMD_CE BIT_ULL(6)
#define ERRCMD_UE BIT_ULL(7)
/* IBECC MMIO base address */
#define IBECC_BASE (res_cfg->ibecc_base)
#define IBECC_ACTIVATE_OFFSET IBECC_BASE
#define IBECC_ACTIVATE_EN BIT(0)
/* IBECC error log */
#define ECC_ERROR_LOG_OFFSET (IBECC_BASE + 0x170)
#define ECC_ERROR_LOG_CE BIT_ULL(62)
#define ECC_ERROR_LOG_UE BIT_ULL(63)
#define ECC_ERROR_LOG_ADDR_SHIFT 5
#define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38)
#define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
/* Host MMIO base address */
#define MCHBAR_OFFSET 0x48
#define MCHBAR_EN BIT_ULL(0)
#define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16)
#define MCHBAR_SIZE 0x10000
/* Parameters for the channel decode stage */
#define MAD_INTER_CHANNEL_OFFSET 0x5000
#define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)
#define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)
#define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)
#define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)
/* Parameters for DRAM decode stage */
#define MAD_INTRA_CH0_OFFSET 0x5004
#define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)
/* DIMM characteristics */
#define MAD_DIMM_CH0_OFFSET 0x500c
#define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)
#define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8)
#define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29)
#define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25)
/* Hash for channel selection */
#define CHANNEL_HASH_OFFSET 0X5024
/* Hash for enhanced channel selection */
#define CHANNEL_EHASH_OFFSET 0X5028
#define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
#define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
#define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28)
static struct res_config {
int num_imc;
u32 ibecc_base;
bool (*ibecc_available)(struct pci_dev *pdev);
/* Convert error address logged in IBECC to system physical address */
u64 (*err_addr_to_sys_addr)(u64 eaddr);
/* Convert error address logged in IBECC to integrated memory controller address */
u64 (*err_addr_to_imc_addr)(u64 eaddr);
} *res_cfg;
struct igen6_imc {
int mc;
struct mem_ctl_info *mci;
struct pci_dev *pdev;
struct device dev;
void __iomem *window;
u64 ch_s_size;
int ch_l_map;
u64 dimm_s_size[NUM_CHANNELS];
u64 dimm_l_size[NUM_CHANNELS];
int dimm_l_map[NUM_CHANNELS];
};
static struct igen6_pvt {
struct igen6_imc imc[NUM_IMC];
} *igen6_pvt;
/* The top of low usable DRAM */
static u32 igen6_tolud;
/* The size of physical memory */
static u64 igen6_tom;
struct decoded_addr {
int mc;
u64 imc_addr;
u64 sys_addr;
int channel_idx;
u64 channel_addr;
int sub_channel_idx;
u64 sub_channel_addr;
};
struct ecclog_node {
struct llist_node llnode;
int mc;
u64 ecclog;
};
/*
* In the NMI handler, the driver uses the lock-less memory allocator
* to allocate memory to store the IBECC error logs and links the logs
* to the lock-less list. Delay printk() and the work of error reporting
* to EDAC core in a worker.
*/
#define ECCLOG_POOL_SIZE PAGE_SIZE
static LLIST_HEAD(ecclog_llist);
static struct gen_pool *ecclog_pool;
static char ecclog_buf[ECCLOG_POOL_SIZE];
static struct irq_work ecclog_irq_work;
static struct work_struct ecclog_work;
/* Compute die IDs for Elkhart Lake with IBECC */
#define DID_EHL_SKU5 0x4514
#define DID_EHL_SKU6 0x4528
#define DID_EHL_SKU7 0x452a
#define DID_EHL_SKU8 0x4516
#define DID_EHL_SKU9 0x452c
#define DID_EHL_SKU10 0x452e
#define DID_EHL_SKU11 0x4532
#define DID_EHL_SKU12 0x4518
#define DID_EHL_SKU13 0x451a
#define DID_EHL_SKU14 0x4534
#define DID_EHL_SKU15 0x4536
static bool ehl_ibecc_available(struct pci_dev *pdev)
{
u32 v;
if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
return false;
return !!(CAPID_C_IBECC & v);
}
static u64 ehl_err_addr_to_sys_addr(u64 eaddr)
{
return eaddr;
}
static u64 ehl_err_addr_to_imc_addr(u64 eaddr)
{
if (eaddr < igen6_tolud)
return eaddr;
if (igen6_tom <= _4GB)
return eaddr + igen6_tolud - _4GB;
if (eaddr < _4GB)
return eaddr + igen6_tolud - igen6_tom;
return eaddr;
}
static struct res_config ehl_cfg = {
.num_imc = 1,
.ibecc_base = 0xdc00,
.ibecc_available = ehl_ibecc_available,
.err_addr_to_sys_addr = ehl_err_addr_to_sys_addr,
.err_addr_to_imc_addr = ehl_err_addr_to_imc_addr,
};
static const struct pci_device_id igen6_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU7), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU8), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU9), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU10), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU11), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU12), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU13), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU14), (kernel_ulong_t)&ehl_cfg },
{ PCI_VDEVICE(INTEL, DID_EHL_SKU15), (kernel_ulong_t)&ehl_cfg },
{ },
};
MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);
static enum dev_type get_width(int dimm_l, u32 mad_dimm)
{
u32 w = dimm_l ? MAD_DIMM_CH_DLW(mad_dimm) :
MAD_DIMM_CH_DSW(mad_dimm);
switch (w) {
case 0:
return DEV_X8;
case 1:
return DEV_X16;
case 2:
return DEV_X32;
default:
return DEV_UNKNOWN;
}
}
static enum mem_type get_memory_type(u32 mad_inter)
{
u32 t = MAD_INTER_CHANNEL_DDR_TYPE(mad_inter);
switch (t) {
case 0:
return MEM_DDR4;
case 1:
return MEM_DDR3;
case 2:
return MEM_LPDDR3;
case 3:
return MEM_LPDDR4;
case 4:
return MEM_WIO2;
default:
return MEM_UNKNOWN;
}
}
static int decode_chan_idx(u64 addr, u64 mask, int intlv_bit)
{
u64 hash_addr = addr & mask, hash = 0;
u64 intlv = (addr >> intlv_bit) & 1;
int i;
for (i = 6; i < 20; i++)
hash ^= (hash_addr >> i) & 1;
return (int)hash ^ intlv;
}
static u64 decode_channel_addr(u64 addr, int intlv_bit)
{
u64 channel_addr;
/* Remove the interleave bit and shift upper part down to fill gap */
channel_addr = GET_BITFIELD(addr, intlv_bit + 1, 63) << intlv_bit;
channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);
return channel_addr;
}
static void decode_addr(u64 addr, u32 hash, u64 s_size, int l_map,
int *idx, u64 *sub_addr)
{
int intlv_bit = CHANNEL_HASH_LSB_MASK_BIT(hash) + 6;
if (addr > 2 * s_size) {
*sub_addr = addr - s_size;
*idx = l_map;
return;
}
if (CHANNEL_HASH_MODE(hash)) {
*sub_addr = decode_channel_addr(addr, intlv_bit);
*idx = decode_chan_idx(addr, CHANNEL_HASH_MASK(hash), intlv_bit);
} else {
*sub_addr = decode_channel_addr(addr, 6);
*idx = GET_BITFIELD(addr, 6, 6);
}
}
static int igen6_decode(struct decoded_addr *res)
{
struct igen6_imc *imc = &igen6_pvt->imc[res->mc];
u64 addr = res->imc_addr, sub_addr, s_size;
int idx, l_map;
u32 hash;
if (addr >= igen6_tom) {
edac_dbg(0, "Address 0x%llx out of range\n", addr);
return -EINVAL;
}
/* Decode channel */
hash = readl(imc->window + CHANNEL_HASH_OFFSET);
s_size = imc->ch_s_size;
l_map = imc->ch_l_map;
decode_addr(addr, hash, s_size, l_map, &idx, &sub_addr);
res->channel_idx = idx;
res->channel_addr = sub_addr;
/* Decode sub-channel/DIMM */
hash = readl(imc->window + CHANNEL_EHASH_OFFSET);
s_size = imc->dimm_s_size[idx];
l_map = imc->dimm_l_map[idx];
decode_addr(res->channel_addr, hash, s_size, l_map, &idx, &sub_addr);
res->sub_channel_idx = idx;
res->sub_channel_addr = sub_addr;
return 0;
}
static void igen6_output_error(struct decoded_addr *res,
struct mem_ctl_info *mci, u64 ecclog)
{
enum hw_event_mc_err_type type = ecclog & ECC_ERROR_LOG_UE ?
HW_EVENT_ERR_UNCORRECTED :
HW_EVENT_ERR_CORRECTED;
edac_mc_handle_error(type, mci, 1,
res->sys_addr >> PAGE_SHIFT,
res->sys_addr & ~PAGE_MASK,
ECC_ERROR_LOG_SYND(ecclog),
res->channel_idx, res->sub_channel_idx,
-1, "", "");
}
static struct gen_pool *ecclog_gen_pool_create(void)
{
struct gen_pool *pool;
pool = gen_pool_create(ilog2(sizeof(struct ecclog_node)), -1);
if (!pool)
return NULL;
if (gen_pool_add(pool, (unsigned long)ecclog_buf, ECCLOG_POOL_SIZE, -1)) {
gen_pool_destroy(pool);
return NULL;
}
return pool;
}
static int ecclog_gen_pool_add(int mc, u64 ecclog)
{
struct ecclog_node *node;
node = (void *)gen_pool_alloc(ecclog_pool, sizeof(*node));
if (!node)
return -ENOMEM;
node->mc = mc;
node->ecclog = ecclog;
llist_add(&node->llnode, &ecclog_llist);
return 0;
}
/*
* Either the memory-mapped I/O status register ECC_ERROR_LOG or the PCI
* configuration space status register ERRSTS can indicate whether a
* correctable error or an uncorrectable error occurred. We only use the
* ECC_ERROR_LOG register to check error type, but need to clear both
* registers to enable future error events.
*/
static u64 ecclog_read_and_clear(struct igen6_imc *imc)
{
u64 ecclog = readq(imc->window + ECC_ERROR_LOG_OFFSET);
if (ecclog & (ECC_ERROR_LOG_CE | ECC_ERROR_LOG_UE)) {
/* Clear CE/UE bits by writing 1s */
writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
return ecclog;
}
return 0;
}
static void errsts_clear(struct igen6_imc *imc)
{
u16 errsts;
if (pci_read_config_word(imc->pdev, ERRSTS_OFFSET, &errsts)) {
igen6_printk(KERN_ERR, "Failed to read ERRSTS\n");
return;
}
/* Clear CE/UE bits by writing 1s */
if (errsts & (ERRSTS_CE | ERRSTS_UE))
pci_write_config_word(imc->pdev, ERRSTS_OFFSET, errsts);
}
static int errcmd_enable_error_reporting(bool enable)
{
struct igen6_imc *imc = &igen6_pvt->imc[0];
u16 errcmd;
int rc;
rc = pci_read_config_word(imc->pdev, ERRCMD_OFFSET, &errcmd);
if (rc)
return rc;
if (enable)
errcmd |= ERRCMD_CE | ERRSTS_UE;
else
errcmd &= ~(ERRCMD_CE | ERRSTS_UE);
rc = pci_write_config_word(imc->pdev, ERRCMD_OFFSET, errcmd);
if (rc)
return rc;
return 0;
}
static int ecclog_handler(void)
{
struct igen6_imc *imc;
int i, n = 0;
u64 ecclog;
for (i = 0; i < res_cfg->num_imc; i++) {
imc = &igen6_pvt->imc[i];
/* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */
ecclog = ecclog_read_and_clear(imc);
if (!ecclog)
continue;
if (!ecclog_gen_pool_add(i, ecclog))
irq_work_queue(&ecclog_irq_work);
n++;
}
return n;
}
static void ecclog_work_cb(struct work_struct *work)
{
struct ecclog_node *node, *tmp;
struct mem_ctl_info *mci;
struct llist_node *head;
struct decoded_addr res;
u64 eaddr;
head = llist_del_all(&ecclog_llist);
if (!head)
return;
llist_for_each_entry_safe(node, tmp, head, llnode) {
memset(&res, 0, sizeof(res));
eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) <<
ECC_ERROR_LOG_ADDR_SHIFT;
res.mc = node->mc;
res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr);
res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr);
mci = igen6_pvt->imc[res.mc].mci;
edac_dbg(2, "MC %d, ecclog = 0x%llx\n", node->mc, node->ecclog);
igen6_mc_printk(mci, KERN_DEBUG, "HANDLING IBECC MEMORY ERROR\n");
igen6_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", res.sys_addr);
if (!igen6_decode(&res))
igen6_output_error(&res, mci, node->ecclog);
gen_pool_free(ecclog_pool, (unsigned long)node, sizeof(*node));
}
}
static void ecclog_irq_work_cb(struct irq_work *irq_work)
{
int i;
for (i = 0; i < res_cfg->num_imc; i++)
errsts_clear(&igen6_pvt->imc[i]);
if (!llist_empty(&ecclog_llist))
schedule_work(&ecclog_work);
}
static int ecclog_nmi_handler(unsigned int cmd, struct pt_regs *regs)
{
unsigned char reason;
if (!ecclog_handler())
return NMI_DONE;
/*
* Both In-Band ECC correctable error and uncorrectable error are
* reported by SERR# NMI. The NMI generic code (see pci_serr_error())
* doesn't clear the bit NMI_REASON_CLEAR_SERR (in port 0x61) to
* re-enable the SERR# NMI after NMI handling. So clear this bit here
* to re-enable SERR# NMI for receiving future In-Band ECC errors.
*/
reason = x86_platform.get_nmi_reason() & NMI_REASON_CLEAR_MASK;
reason |= NMI_REASON_CLEAR_SERR;
outb(reason, NMI_REASON_PORT);
reason &= ~NMI_REASON_CLEAR_SERR;
outb(reason, NMI_REASON_PORT);
return NMI_HANDLED;
}
static bool igen6_check_ecc(struct igen6_imc *imc)
{
u32 activate = readl(imc->window + IBECC_ACTIVATE_OFFSET);
return !!(activate & IBECC_ACTIVATE_EN);
}
static int igen6_get_dimm_config(struct mem_ctl_info *mci)
{
struct igen6_imc *imc = mci->pvt_info;
u32 mad_inter, mad_intra, mad_dimm;
int i, j, ndimms, mc = imc->mc;
struct dimm_info *dimm;
enum mem_type mtype;
enum dev_type dtype;
u64 dsize;
bool ecc;
edac_dbg(2, "\n");
mad_inter = readl(imc->window + MAD_INTER_CHANNEL_OFFSET);
mtype = get_memory_type(mad_inter);
ecc = igen6_check_ecc(imc);
imc->ch_s_size = MAD_INTER_CHANNEL_CH_S_SIZE(mad_inter);
imc->ch_l_map = MAD_INTER_CHANNEL_CH_L_MAP(mad_inter);
for (i = 0; i < NUM_CHANNELS; i++) {
mad_intra = readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4);
mad_dimm = readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4);
imc->dimm_l_size[i] = MAD_DIMM_CH_DIMM_L_SIZE(mad_dimm);
imc->dimm_s_size[i] = MAD_DIMM_CH_DIMM_S_SIZE(mad_dimm);
imc->dimm_l_map[i] = MAD_INTRA_CH_DIMM_L_MAP(mad_intra);
ndimms = 0;
for (j = 0; j < NUM_DIMMS; j++) {
dimm = edac_get_dimm(mci, i, j, 0);
if (j ^ imc->dimm_l_map[i]) {
dtype = get_width(0, mad_dimm);
dsize = imc->dimm_s_size[i];
} else {
dtype = get_width(1, mad_dimm);
dsize = imc->dimm_l_size[i];
}
if (!dsize)
continue;
dimm->grain = 64;
dimm->mtype = mtype;
dimm->dtype = dtype;
dimm->nr_pages = MiB_TO_PAGES(dsize >> 20);
dimm->edac_mode = EDAC_SECDED;
snprintf(dimm->label, sizeof(dimm->label),
"MC#%d_Chan#%d_DIMM#%d", mc, i, j);
edac_dbg(0, "MC %d, Channel %d, DIMM %d, Size %llu MiB (%u pages)\n",
mc, i, j, dsize >> 20, dimm->nr_pages);
ndimms++;
}
if (ndimms && !ecc) {
igen6_printk(KERN_ERR, "MC%d In-Band ECC is disabled\n", mc);
return -ENODEV;
}
}
return 0;
}
#ifdef CONFIG_EDAC_DEBUG
/* Top of upper usable DRAM */
static u64 igen6_touud;
#define TOUUD_OFFSET 0xa8
static void igen6_reg_dump(struct igen6_imc *imc)
{
int i;
edac_dbg(2, "CHANNEL_HASH : 0x%x\n",
readl(imc->window + CHANNEL_HASH_OFFSET));
edac_dbg(2, "CHANNEL_EHASH : 0x%x\n",
readl(imc->window + CHANNEL_EHASH_OFFSET));
edac_dbg(2, "MAD_INTER_CHANNEL: 0x%x\n",
readl(imc->window + MAD_INTER_CHANNEL_OFFSET));
edac_dbg(2, "ECC_ERROR_LOG : 0x%llx\n",
readq(imc->window + ECC_ERROR_LOG_OFFSET));
for (i = 0; i < NUM_CHANNELS; i++) {
edac_dbg(2, "MAD_INTRA_CH%d : 0x%x\n", i,
readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4));
edac_dbg(2, "MAD_DIMM_CH%d : 0x%x\n", i,
readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4));
}
edac_dbg(2, "TOLUD : 0x%x", igen6_tolud);
edac_dbg(2, "TOUUD : 0x%llx", igen6_touud);
edac_dbg(2, "TOM : 0x%llx", igen6_tom);
}
static struct dentry *igen6_test;
static int debugfs_u64_set(void *data, u64 val)
{
u64 ecclog;
if ((val >= igen6_tolud && val < _4GB) || val >= igen6_touud) {
edac_dbg(0, "Address 0x%llx out of range\n", val);
return 0;
}
pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
val >>= ECC_ERROR_LOG_ADDR_SHIFT;
ecclog = (val << ECC_ERROR_LOG_ADDR_SHIFT) | ECC_ERROR_LOG_CE;
if (!ecclog_gen_pool_add(0, ecclog))
irq_work_queue(&ecclog_irq_work);
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
static void igen6_debug_setup(void)
{
igen6_test = edac_debugfs_create_dir("igen6_test");
if (!igen6_test)
return;
if (!edac_debugfs_create_file("addr", 0200, igen6_test,
NULL, &fops_u64_wo)) {
debugfs_remove(igen6_test);
igen6_test = NULL;
}
}
static void igen6_debug_teardown(void)
{
debugfs_remove_recursive(igen6_test);
}
#else
static void igen6_reg_dump(struct igen6_imc *imc) {}
static void igen6_debug_setup(void) {}
static void igen6_debug_teardown(void) {}
#endif
static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
{
union {
u64 v;
struct {
u32 v_lo;
u32 v_hi;
};
} u;
edac_dbg(2, "\n");
if (!res_cfg->ibecc_available(pdev)) {
edac_dbg(2, "No In-Band ECC IP\n");
goto fail;
}
if (pci_read_config_dword(pdev, TOLUD_OFFSET, &igen6_tolud)) {
igen6_printk(KERN_ERR, "Failed to read TOLUD\n");
goto fail;
}
igen6_tolud &= GENMASK(31, 20);
if (pci_read_config_dword(pdev, TOM_OFFSET, &u.v_lo)) {
igen6_printk(KERN_ERR, "Failed to read lower TOM\n");
goto fail;
}
if (pci_read_config_dword(pdev, TOM_OFFSET + 4, &u.v_hi)) {
igen6_printk(KERN_ERR, "Failed to read upper TOM\n");
goto fail;
}
igen6_tom = u.v & GENMASK_ULL(38, 20);
if (pci_read_config_dword(pdev, MCHBAR_OFFSET, &u.v_lo)) {
igen6_printk(KERN_ERR, "Failed to read lower MCHBAR\n");
goto fail;
}
if (pci_read_config_dword(pdev, MCHBAR_OFFSET + 4, &u.v_hi)) {
igen6_printk(KERN_ERR, "Failed to read upper MCHBAR\n");
goto fail;
}
if (!(u.v & MCHBAR_EN)) {
igen6_printk(KERN_ERR, "MCHBAR is disabled\n");
goto fail;
}
*mchbar = MCHBAR_BASE(u.v);
#ifdef CONFIG_EDAC_DEBUG
if (pci_read_config_dword(pdev, TOUUD_OFFSET, &u.v_lo))
edac_dbg(2, "Failed to read lower TOUUD\n");
else if (pci_read_config_dword(pdev, TOUUD_OFFSET + 4, &u.v_hi))
edac_dbg(2, "Failed to read upper TOUUD\n");
else
igen6_touud = u.v & GENMASK_ULL(38, 20);
#endif
return 0;
fail:
return -ENODEV;
}
static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev)
{
struct edac_mc_layer layers[2];
struct mem_ctl_info *mci;
struct igen6_imc *imc;
void __iomem *window;
int rc;
edac_dbg(2, "\n");
mchbar += mc * MCHBAR_SIZE;
window = ioremap(mchbar, MCHBAR_SIZE);
if (!window) {
igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);
return -ENODEV;
}
layers[0].type = EDAC_MC_LAYER_CHANNEL;
layers[0].size = NUM_CHANNELS;
layers[0].is_virt_csrow = false;
layers[1].type = EDAC_MC_LAYER_SLOT;
layers[1].size = NUM_DIMMS;
layers[1].is_virt_csrow = true;
mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
if (!mci) {
rc = -ENOMEM;
goto fail;
}
mci->ctl_name = kasprintf(GFP_KERNEL, "Intel_client_SoC MC#%d", mc);
if (!mci->ctl_name) {
rc = -ENOMEM;
goto fail2;
}
mci->mtype_cap = MEM_FLAG_LPDDR4 | MEM_FLAG_DDR4;
mci->edac_ctl_cap = EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
mci->dev_name = pci_name(pdev);
mci->pvt_info = &igen6_pvt->imc[mc];
imc = mci->pvt_info;
device_initialize(&imc->dev);
/*
* EDAC core uses mci->pdev(pointer of structure device) as
* memory controller ID. The client SoCs attach one or more
* memory controllers to single pci_dev (single pci_dev->dev
* can be for multiple memory controllers).
*
* To make mci->pdev unique, assign pci_dev->dev to mci->pdev
* for the first memory controller and assign a unique imc->dev
* to mci->pdev for each non-first memory controller.
*/
mci->pdev = mc ? &imc->dev : &pdev->dev;
imc->mc = mc;
imc->pdev = pdev;
imc->window = window;
igen6_reg_dump(imc);
rc = igen6_get_dimm_config(mci);
if (rc)
goto fail3;
rc = edac_mc_add_mc(mci);
if (rc) {
igen6_printk(KERN_ERR, "Failed to register mci#%d\n", mc);
goto fail3;
}
imc->mci = mci;
return 0;
fail3:
kfree(mci->ctl_name);
fail2:
edac_mc_free(mci);
fail:
iounmap(window);
return rc;
}
static void igen6_unregister_mcis(void)
{
struct mem_ctl_info *mci;
struct igen6_imc *imc;
int i;
edac_dbg(2, "\n");
for (i = 0; i < res_cfg->num_imc; i++) {
imc = &igen6_pvt->imc[i];
mci = imc->mci;
if (!mci)
continue;
edac_mc_del_mc(mci->pdev);
kfree(mci->ctl_name);
edac_mc_free(mci);
iounmap(imc->window);
}
}
static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
u64 mchbar;
int i, rc;
edac_dbg(2, "\n");
igen6_pvt = kzalloc(sizeof(*igen6_pvt), GFP_KERNEL);
if (!igen6_pvt)
return -ENOMEM;
res_cfg = (struct res_config *)ent->driver_data;
rc = igen6_pci_setup(pdev, &mchbar);
if (rc)
goto fail;
for (i = 0; i < res_cfg->num_imc; i++) {
rc = igen6_register_mci(i, mchbar, pdev);
if (rc)
goto fail2;
}
ecclog_pool = ecclog_gen_pool_create();
if (!ecclog_pool) {
rc = -ENOMEM;
goto fail2;
}
INIT_WORK(&ecclog_work, ecclog_work_cb);
init_irq_work(&ecclog_irq_work, ecclog_irq_work_cb);
/* Check if any pending errors before registering the NMI handler */
ecclog_handler();
rc = register_nmi_handler(NMI_SERR, ecclog_nmi_handler,
0, IGEN6_NMI_NAME);
if (rc) {
igen6_printk(KERN_ERR, "Failed to register NMI handler\n");
goto fail3;
}
/* Enable error reporting */
rc = errcmd_enable_error_reporting(true);
if (rc) {
igen6_printk(KERN_ERR, "Failed to enable error reporting\n");
goto fail4;
}
igen6_debug_setup();
return 0;
fail4:
unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
fail3:
gen_pool_destroy(ecclog_pool);
fail2:
igen6_unregister_mcis();
fail:
kfree(igen6_pvt);
return rc;
}
static void igen6_remove(struct pci_dev *pdev)
{
edac_dbg(2, "\n");
igen6_debug_teardown();
errcmd_enable_error_reporting(false);
unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
irq_work_sync(&ecclog_irq_work);
flush_work(&ecclog_work);
gen_pool_destroy(ecclog_pool);
igen6_unregister_mcis();
kfree(igen6_pvt);
}
static struct pci_driver igen6_driver = {
.name = EDAC_MOD_STR,
.probe = igen6_probe,
.remove = igen6_remove,
.id_table = igen6_pci_tbl,
};
static int __init igen6_init(void)
{
const char *owner;
int rc;
edac_dbg(2, "\n");
owner = edac_get_owner();
if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
return -ENODEV;
edac_op_state = EDAC_OPSTATE_NMI;
rc = pci_register_driver(&igen6_driver);
if (rc)
return rc;
igen6_printk(KERN_INFO, "%s\n", IGEN6_REVISION);
return 0;
}
static void __exit igen6_exit(void)
{
edac_dbg(2, "\n");
pci_unregister_driver(&igen6_driver);
}
module_init(igen6_init);
module_exit(igen6_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qiuxu Zhuo");
MODULE_DESCRIPTION("MC Driver for Intel client SoC using In-Band ECC");

883
drivers/edac/mv64x60_edac.c
View File

@ -1,883 +0,0 @@
/*
* Marvell MV64x60 Memory Controller kernel module for PPC platforms
*
* Author: Dave Jiang <djiang@mvista.com>
*
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/edac.h>
#include <linux/gfp.h>
#include "edac_module.h"
#include "mv64x60_edac.h"
static const char *mv64x60_ctl_name = "MV64x60";
static int edac_dev_idx;
static int edac_pci_idx;
static int edac_mc_idx;
/*********************** PCI err device **********************************/
#ifdef CONFIG_PCI
static void mv64x60_pci_check(struct edac_pci_ctl_info *pci)
{
struct mv64x60_pci_pdata *pdata = pci->pvt_info;
u32 cause;
cause = readl(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE);
if (!cause)
return;
printk(KERN_ERR "Error in PCI %d Interface\n", pdata->pci_hose);
printk(KERN_ERR "Cause register: 0x%08x\n", cause);
printk(KERN_ERR "Address Low: 0x%08x\n",
readl(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_LO));
printk(KERN_ERR "Address High: 0x%08x\n",
readl(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_HI));
printk(KERN_ERR "Attribute: 0x%08x\n",
readl(pdata->pci_vbase + MV64X60_PCI_ERROR_ATTR));
printk(KERN_ERR "Command: 0x%08x\n",
readl(pdata->pci_vbase + MV64X60_PCI_ERROR_CMD));
writel(~cause, pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE);
if (cause & MV64X60_PCI_PE_MASK)
edac_pci_handle_pe(pci, pci->ctl_name);
if (!(cause & MV64X60_PCI_PE_MASK))
edac_pci_handle_npe(pci, pci->ctl_name);
}
static irqreturn_t mv64x60_pci_isr(int irq, void *dev_id)
{
struct edac_pci_ctl_info *pci = dev_id;
struct mv64x60_pci_pdata *pdata = pci->pvt_info;
u32 val;
val = readl(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE);
if (!val)
return IRQ_NONE;
mv64x60_pci_check(pci);
return IRQ_HANDLED;
}
/*
* Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
* errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
* well. IOW, don't set bit 0.
*/
/* Erratum FEr PCI-#16: clear bit 0 of PCI SERRn Mask reg. */
static int __init mv64x60_pci_fixup(struct platform_device *pdev)
{
struct resource *r;
void __iomem *pci_serr;
r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"PCI err regs\n", __func__);
return -ENOENT;
}
pci_serr = ioremap(r->start, resource_size(r));
if (!pci_serr)
return -ENOMEM;
writel(readl(pci_serr) & ~0x1, pci_serr);
iounmap(pci_serr);
return 0;
}
static int mv64x60_pci_err_probe(struct platform_device *pdev)
{
struct edac_pci_ctl_info *pci;
struct mv64x60_pci_pdata *pdata;
struct resource *r;
int res = 0;
if (!devres_open_group(&pdev->dev, mv64x60_pci_err_probe, GFP_KERNEL))
return -ENOMEM;
pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mv64x60_pci_err");
if (!pci)
return -ENOMEM;
pdata = pci->pvt_info;
pdata->pci_hose = pdev->id;
pdata->name = "mv64x60_pci_err";
platform_set_drvdata(pdev, pci);
pci->dev = &pdev->dev;
pci->dev_name = dev_name(&pdev->dev);
pci->mod_name = EDAC_MOD_STR;
pci->ctl_name = pdata->name;
if (edac_op_state == EDAC_OPSTATE_POLL)
pci->edac_check = mv64x60_pci_check;
pdata->edac_idx = edac_pci_idx++;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"PCI err regs\n", __func__);
res = -ENOENT;
goto err;
}
if (!devm_request_mem_region(&pdev->dev,
r->start,
resource_size(r),
pdata->name)) {
printk(KERN_ERR "%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
}
pdata->pci_vbase = devm_ioremap(&pdev->dev,
r->start,
resource_size(r));
if (!pdata->pci_vbase) {
printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
res = -ENOMEM;
goto err;
}
res = mv64x60_pci_fixup(pdev);
if (res < 0) {
printk(KERN_ERR "%s: PCI fixup failed\n", __func__);
goto err;
}
writel(0, pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE);
writel(0, pdata->pci_vbase + MV64X60_PCI_ERROR_MASK);
writel(MV64X60_PCIx_ERR_MASK_VAL,
pdata->pci_vbase + MV64X60_PCI_ERROR_MASK);
if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
edac_dbg(3, "failed edac_pci_add_device()\n");
goto err;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = platform_get_irq(pdev, 0);
res = devm_request_irq(&pdev->dev,
pdata->irq,
mv64x60_pci_isr,
0,
"[EDAC] PCI err",
pci);
if (res < 0) {
printk(KERN_ERR "%s: Unable to request irq %d for "
"MV64x60 PCI ERR\n", __func__, pdata->irq);
res = -ENODEV;
goto err2;
}
printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
pdata->irq);
}
devres_remove_group(&pdev->dev, mv64x60_pci_err_probe);
/* get this far and it's successful */
edac_dbg(3, "success\n");
return 0;
err2:
edac_pci_del_device(&pdev->dev);
err:
edac_pci_free_ctl_info(pci);
devres_release_group(&pdev->dev, mv64x60_pci_err_probe);
return res;
}
static int mv64x60_pci_err_remove(struct platform_device *pdev)
{
struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
edac_dbg(0, "\n");
edac_pci_del_device(&pdev->dev);
edac_pci_free_ctl_info(pci);
return 0;
}
static struct platform_driver mv64x60_pci_err_driver = {
.probe = mv64x60_pci_err_probe,
.remove = mv64x60_pci_err_remove,
.driver = {
.name = "mv64x60_pci_err",
}
};
#endif /* CONFIG_PCI */
/*********************** SRAM err device **********************************/
static void mv64x60_sram_check(struct edac_device_ctl_info *edac_dev)
{
struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info;
u32 cause;
cause = readl(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE);
if (!cause)
return;
printk(KERN_ERR "Error in internal SRAM\n");
printk(KERN_ERR "Cause register: 0x%08x\n", cause);
printk(KERN_ERR "Address Low: 0x%08x\n",
readl(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_LO));
printk(KERN_ERR "Address High: 0x%08x\n",
readl(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_HI));
printk(KERN_ERR "Data Low: 0x%08x\n",
readl(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_LO));
printk(KERN_ERR "Data High: 0x%08x\n",
readl(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_HI));
printk(KERN_ERR "Parity: 0x%08x\n",
readl(pdata->sram_vbase + MV64X60_SRAM_ERR_PARITY));
writel(0, pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE);
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
}
static irqreturn_t mv64x60_sram_isr(int irq, void *dev_id)
{
struct edac_device_ctl_info *edac_dev = dev_id;
struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info;
u32 cause;
cause = readl(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE);
if (!cause)
return IRQ_NONE;
mv64x60_sram_check(edac_dev);
return IRQ_HANDLED;
}
static int mv64x60_sram_err_probe(struct platform_device *pdev)
{
struct edac_device_ctl_info *edac_dev;
struct mv64x60_sram_pdata *pdata;
struct resource *r;
int res = 0;
if (!devres_open_group(&pdev->dev, mv64x60_sram_err_probe, GFP_KERNEL))
return -ENOMEM;
edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
"sram", 1, NULL, 0, 0, NULL, 0,
edac_dev_idx);
if (!edac_dev) {
devres_release_group(&pdev->dev, mv64x60_sram_err_probe);
return -ENOMEM;
}
pdata = edac_dev->pvt_info;
pdata->name = "mv64x60_sram_err";
edac_dev->dev = &pdev->dev;
platform_set_drvdata(pdev, edac_dev);
edac_dev->dev_name = dev_name(&pdev->dev);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"SRAM err regs\n", __func__);
res = -ENOENT;
goto err;
}
if (!devm_request_mem_region(&pdev->dev,
r->start,
resource_size(r),
pdata->name)) {
printk(KERN_ERR "%s: Error while request mem region\n",
__func__);
res = -EBUSY;
goto err;
}
pdata->sram_vbase = devm_ioremap(&pdev->dev,
r->start,
resource_size(r));
if (!pdata->sram_vbase) {
printk(KERN_ERR "%s: Unable to setup SRAM err regs\n",
__func__);
res = -ENOMEM;
goto err;
}
/* setup SRAM err registers */
writel(0, pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE);
edac_dev->mod_name = EDAC_MOD_STR;
edac_dev->ctl_name = pdata->name;
if (edac_op_state == EDAC_OPSTATE_POLL)
edac_dev->edac_check = mv64x60_sram_check;
pdata->edac_idx = edac_dev_idx++;
if (edac_device_add_device(edac_dev) > 0) {
edac_dbg(3, "failed edac_device_add_device()\n");
goto err;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = platform_get_irq(pdev, 0);
res = devm_request_irq(&pdev->dev,
pdata->irq,
mv64x60_sram_isr,
0,
"[EDAC] SRAM err",
edac_dev);
if (res < 0) {
printk(KERN_ERR
"%s: Unable to request irq %d for "
"MV64x60 SRAM ERR\n", __func__, pdata->irq);
res = -ENODEV;
goto err2;
}
printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for SRAM Err\n",
pdata->irq);
}
devres_remove_group(&pdev->dev, mv64x60_sram_err_probe);
/* get this far and it's successful */
edac_dbg(3, "success\n");
return 0;
err2:
edac_device_del_device(&pdev->dev);
err:
devres_release_group(&pdev->dev, mv64x60_sram_err_probe);
edac_device_free_ctl_info(edac_dev);
return res;
}
static int mv64x60_sram_err_remove(struct platform_device *pdev)
{
struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
edac_dbg(0, "\n");
edac_device_del_device(&pdev->dev);
edac_device_free_ctl_info(edac_dev);
return 0;
}
static struct platform_driver mv64x60_sram_err_driver = {
.probe = mv64x60_sram_err_probe,
.remove = mv64x60_sram_err_remove,
.driver = {
.name = "mv64x60_sram_err",
}
};
/*********************** CPU err device **********************************/
static void mv64x60_cpu_check(struct edac_device_ctl_info *edac_dev)
{
struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info;
u32 cause;
cause = readl(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) &
MV64x60_CPU_CAUSE_MASK;
if (!cause)
return;
printk(KERN_ERR "Error on CPU interface\n");
printk(KERN_ERR "Cause register: 0x%08x\n", cause);
printk(KERN_ERR "Address Low: 0x%08x\n",
readl(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_LO));
printk(KERN_ERR "Address High: 0x%08x\n",
readl(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_HI));
printk(KERN_ERR "Data Low: 0x%08x\n",
readl(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_LO));
printk(KERN_ERR "Data High: 0x%08x\n",
readl(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_HI));
printk(KERN_ERR "Parity: 0x%08x\n",
readl(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_PARITY));
writel(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE);
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
}
static irqreturn_t mv64x60_cpu_isr(int irq, void *dev_id)
{
struct edac_device_ctl_info *edac_dev = dev_id;
struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info;
u32 cause;
cause = readl(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) &
MV64x60_CPU_CAUSE_MASK;
if (!cause)
return IRQ_NONE;
mv64x60_cpu_check(edac_dev);
return IRQ_HANDLED;
}
static int mv64x60_cpu_err_probe(struct platform_device *pdev)
{
struct edac_device_ctl_info *edac_dev;
struct resource *r;
struct mv64x60_cpu_pdata *pdata;
int res = 0;
if (!devres_open_group(&pdev->dev, mv64x60_cpu_err_probe, GFP_KERNEL))
return -ENOMEM;
edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
"cpu", 1, NULL, 0, 0, NULL, 0,
edac_dev_idx);
if (!edac_dev) {
devres_release_group(&pdev->dev, mv64x60_cpu_err_probe);
return -ENOMEM;
}
pdata = edac_dev->pvt_info;
pdata->name = "mv64x60_cpu_err";
edac_dev->dev = &pdev->dev;
platform_set_drvdata(pdev, edac_dev);
edac_dev->dev_name = dev_name(&pdev->dev);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"CPU err regs\n", __func__);
res = -ENOENT;
goto err;
}
if (!devm_request_mem_region(&pdev->dev,
r->start,
resource_size(r),
pdata->name)) {
printk(KERN_ERR "%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
}
pdata->cpu_vbase[0] = devm_ioremap(&pdev->dev,
r->start,
resource_size(r));
if (!pdata->cpu_vbase[0]) {
printk(KERN_ERR "%s: Unable to setup CPU err regs\n", __func__);
res = -ENOMEM;
goto err;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"CPU err regs\n", __func__);
res = -ENOENT;
goto err;
}
if (!devm_request_mem_region(&pdev->dev,
r->start,
resource_size(r),
pdata->name)) {
printk(KERN_ERR "%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
}
pdata->cpu_vbase[1] = devm_ioremap(&pdev->dev,
r->start,
resource_size(r));
if (!pdata->cpu_vbase[1]) {
printk(KERN_ERR "%s: Unable to setup CPU err regs\n", __func__);
res = -ENOMEM;
goto err;
}
/* setup CPU err registers */
writel(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE);
writel(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK);
writel(0x000000ff, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK);
edac_dev->mod_name = EDAC_MOD_STR;
edac_dev->ctl_name = pdata->name;
if (edac_op_state == EDAC_OPSTATE_POLL)
edac_dev->edac_check = mv64x60_cpu_check;
pdata->edac_idx = edac_dev_idx++;
if (edac_device_add_device(edac_dev) > 0) {
edac_dbg(3, "failed edac_device_add_device()\n");
goto err;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = platform_get_irq(pdev, 0);
res = devm_request_irq(&pdev->dev,
pdata->irq,
mv64x60_cpu_isr,
0,
"[EDAC] CPU err",
edac_dev);
if (res < 0) {
printk(KERN_ERR
"%s: Unable to request irq %d for MV64x60 "
"CPU ERR\n", __func__, pdata->irq);
res = -ENODEV;
goto err2;
}
printk(KERN_INFO EDAC_MOD_STR
" acquired irq %d for CPU Err\n", pdata->irq);
}
devres_remove_group(&pdev->dev, mv64x60_cpu_err_probe);
/* get this far and it's successful */
edac_dbg(3, "success\n");
return 0;
err2:
edac_device_del_device(&pdev->dev);
err:
devres_release_group(&pdev->dev, mv64x60_cpu_err_probe);
edac_device_free_ctl_info(edac_dev);
return res;
}
static int mv64x60_cpu_err_remove(struct platform_device *pdev)
{
struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
edac_dbg(0, "\n");
edac_device_del_device(&pdev->dev);
edac_device_free_ctl_info(edac_dev);
return 0;
}
static struct platform_driver mv64x60_cpu_err_driver = {
.probe = mv64x60_cpu_err_probe,
.remove = mv64x60_cpu_err_remove,
.driver = {
.name = "mv64x60_cpu_err",
}
};
/*********************** DRAM err device **********************************/
static void mv64x60_mc_check(struct mem_ctl_info *mci)
{
struct mv64x60_mc_pdata *pdata = mci->pvt_info;
u32 reg;
u32 err_addr;
u32 sdram_ecc;
u32 comp_ecc;
u32 syndrome;
reg = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR);
if (!reg)
return;
err_addr = reg & ~0x3;
sdram_ecc = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_RCVD);
comp_ecc = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CALC);
syndrome = sdram_ecc ^ comp_ecc;
/* first bit clear in ECC Err Reg, 1 bit error, correctable by HW */
if (!(reg & 0x1))
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
err_addr >> PAGE_SHIFT,
err_addr & PAGE_MASK, syndrome,
0, 0, -1,
mci->ctl_name, "");
else /* 2 bit error, UE */
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
err_addr >> PAGE_SHIFT,
err_addr & PAGE_MASK, 0,
0, 0, -1,
mci->ctl_name, "");
/* clear the error */
writel(0, pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR);
}
static irqreturn_t mv64x60_mc_isr(int irq, void *dev_id)
{
struct mem_ctl_info *mci = dev_id;
struct mv64x60_mc_pdata *pdata = mci->pvt_info;
u32 reg;
reg = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR);
if (!reg)
return IRQ_NONE;
/* writing 0's to the ECC err addr in check function clears irq */
mv64x60_mc_check(mci);
return IRQ_HANDLED;
}
static void get_total_mem(struct mv64x60_mc_pdata *pdata)
{
struct device_node *np = NULL;
const unsigned int *reg;
np = of_find_node_by_type(NULL, "memory");
if (!np)
return;
reg = of_get_property(np, "reg", NULL);
pdata->total_mem = reg[1];
}
static void mv64x60_init_csrows(struct mem_ctl_info *mci,
struct mv64x60_mc_pdata *pdata)
{
struct csrow_info *csrow;
struct dimm_info *dimm;
u32 devtype;
u32 ctl;
get_total_mem(pdata);
ctl = readl(pdata->mc_vbase + MV64X60_SDRAM_CONFIG);
csrow = mci->csrows[0];
dimm = csrow->channels[0]->dimm;
dimm->nr_pages = pdata->total_mem >> PAGE_SHIFT;
dimm->grain = 8;
dimm->mtype = (ctl & MV64X60_SDRAM_REGISTERED) ? MEM_RDDR : MEM_DDR;
devtype = (ctl >> 20) & 0x3;
switch (devtype) {
case 0x0:
dimm->dtype = DEV_X32;
break;
case 0x2: /* could be X8 too, but no way to tell */
dimm->dtype = DEV_X16;
break;
case 0x3:
dimm->dtype = DEV_X4;
break;
default:
dimm->dtype = DEV_UNKNOWN;
break;
}
dimm->edac_mode = EDAC_SECDED;
}
static int mv64x60_mc_err_probe(struct platform_device *pdev)
{
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2];
struct mv64x60_mc_pdata *pdata;
struct resource *r;
u32 ctl;
int res = 0;
if (!devres_open_group(&pdev->dev, mv64x60_mc_err_probe, GFP_KERNEL))
return -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = 1;
layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = 1;
layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
sizeof(struct mv64x60_mc_pdata));
if (!mci) {
printk(KERN_ERR "%s: No memory for CPU err\n", __func__);
devres_release_group(&pdev->dev, mv64x60_mc_err_probe);
return -ENOMEM;
}
pdata = mci->pvt_info;
mci->pdev = &pdev->dev;
platform_set_drvdata(pdev, mci);
pdata->name = "mv64x60_mc_err";
mci->dev_name = dev_name(&pdev->dev);
pdata->edac_idx = edac_mc_idx++;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
printk(KERN_ERR "%s: Unable to get resource for "
"MC err regs\n", __func__);
res = -ENOENT;
goto err;
}
if (!devm_request_mem_region(&pdev->dev,
r->start,
resource_size(r),
pdata->name)) {
printk(KERN_ERR "%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
}
pdata->mc_vbase = devm_ioremap(&pdev->dev,
r->start,
resource_size(r));
if (!pdata->mc_vbase) {
printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
res = -ENOMEM;
goto err;
}
ctl = readl(pdata->mc_vbase + MV64X60_SDRAM_CONFIG);
if (!(ctl & MV64X60_SDRAM_ECC)) {
/* Non-ECC RAM? */
printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
res = -ENODEV;
goto err;
}
edac_dbg(3, "init mci\n");
mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
mci->ctl_name = mv64x60_ctl_name;
if (edac_op_state == EDAC_OPSTATE_POLL)
mci->edac_check = mv64x60_mc_check;
mci->ctl_page_to_phys = NULL;
mci->scrub_mode = SCRUB_SW_SRC;
mv64x60_init_csrows(mci, pdata);
/* setup MC registers */
writel(0, pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR);
ctl = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL);
ctl = (ctl & 0xff00ffff) | 0x10000;
writel(ctl, pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL);
res = edac_mc_add_mc(mci);
if (res) {
edac_dbg(3, "failed edac_mc_add_mc()\n");
goto err;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
/* acquire interrupt that reports errors */
pdata->irq = platform_get_irq(pdev, 0);
res = devm_request_irq(&pdev->dev,
pdata->irq,
mv64x60_mc_isr,
0,
"[EDAC] MC err",
mci);
if (res < 0) {
printk(KERN_ERR "%s: Unable to request irq %d for "
"MV64x60 DRAM ERR\n", __func__, pdata->irq);
res = -ENODEV;
goto err2;
}
printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC Err\n",
pdata->irq);
}
/* get this far and it's successful */
edac_dbg(3, "success\n");
return 0;
err2:
edac_mc_del_mc(&pdev->dev);
err:
devres_release_group(&pdev->dev, mv64x60_mc_err_probe);
edac_mc_free(mci);
return res;
}
static int mv64x60_mc_err_remove(struct platform_device *pdev)
{
struct mem_ctl_info *mci = platform_get_drvdata(pdev);
edac_dbg(0, "\n");
edac_mc_del_mc(&pdev->dev);
edac_mc_free(mci);
return 0;
}
static struct platform_driver mv64x60_mc_err_driver = {
.probe = mv64x60_mc_err_probe,
.remove = mv64x60_mc_err_remove,
.driver = {
.name = "mv64x60_mc_err",
}
};
static struct platform_driver * const drivers[] = {
&mv64x60_mc_err_driver,
&mv64x60_cpu_err_driver,
&mv64x60_sram_err_driver,
#ifdef CONFIG_PCI
&mv64x60_pci_err_driver,
#endif
};
static int __init mv64x60_edac_init(void)
{
printk(KERN_INFO "Marvell MV64x60 EDAC driver " MV64x60_REVISION "\n");
printk(KERN_INFO "\t(C) 2006-2007 MontaVista Software\n");
/* make sure error reporting method is sane */
switch (edac_op_state) {
case EDAC_OPSTATE_POLL:
case EDAC_OPSTATE_INT:
break;
default:
edac_op_state = EDAC_OPSTATE_INT;
break;
}
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
module_init(mv64x60_edac_init);
static void __exit mv64x60_edac_exit(void)
{
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
module_exit(mv64x60_edac_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Montavista Software, Inc.");
module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state,
"EDAC Error Reporting state: 0=Poll, 2=Interrupt");

114
drivers/edac/mv64x60_edac.h
View File

@ -1,114 +0,0 @@
/*
* EDAC defs for Marvell MV64x60 bridge chip
*
* Author: Dave Jiang <djiang@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#ifndef _MV64X60_EDAC_H_
#define _MV64X60_EDAC_H_
#define MV64x60_REVISION " Ver: 2.0.0"
#define EDAC_MOD_STR "MV64x60_edac"
#define mv64x60_printk(level, fmt, arg...) \
edac_printk(level, "MV64x60", fmt, ##arg)
#define mv64x60_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg)
/* CPU Error Report Registers */
#define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
#define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
#define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
#define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
#define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
#define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
#define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
#define MV64x60_CPU_CAUSE_MASK 0x07ffffff
/* SRAM Error Report Registers */
#define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
#define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */
#define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */
#define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */
#define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */
#define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */
/* SDRAM Controller Registers */
#define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */
#define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */
#define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */
#define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */
#define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */
#define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */
#define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */
#define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */
#define MV64X60_SDRAM_REGISTERED 0x20000
#define MV64X60_SDRAM_ECC 0x40000
#ifdef CONFIG_PCI
/*
* Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
* errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
* well. IOW, don't set bit 0.
*/
#define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24
/* Register offsets from PCIx error address low register */
#define MV64X60_PCI_ERROR_ADDR_LO 0x00
#define MV64X60_PCI_ERROR_ADDR_HI 0x04
#define MV64X60_PCI_ERROR_ATTR 0x08
#define MV64X60_PCI_ERROR_CMD 0x10
#define MV64X60_PCI_ERROR_CAUSE 0x18
#define MV64X60_PCI_ERROR_MASK 0x1c
#define MV64X60_PCI_ERR_SWrPerr 0x0002
#define MV64X60_PCI_ERR_SRdPerr 0x0004
#define MV64X60_PCI_ERR_MWrPerr 0x0020
#define MV64X60_PCI_ERR_MRdPerr 0x0040
#define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \
MV64X60_PCI_ERR_SRdPerr | \
MV64X60_PCI_ERR_MWrPerr | \
MV64X60_PCI_ERR_MRdPerr)
struct mv64x60_pci_pdata {
int pci_hose;
void __iomem *pci_vbase;
char *name;
int irq;
int edac_idx;
};
#endif /* CONFIG_PCI */
struct mv64x60_mc_pdata {
void __iomem *mc_vbase;
int total_mem;
char *name;
int irq;
int edac_idx;
};
struct mv64x60_cpu_pdata {
void __iomem *cpu_vbase[2];
char *name;
int irq;
int edac_idx;
};
struct mv64x60_sram_pdata {
void __iomem *sram_vbase;
char *name;
int irq;
int edac_idx;
};
#endif

1
drivers/edac/r82600_edac.c
View File

@ -204,7 +204,6 @@ static void r82600_check(struct mem_ctl_info *mci)
{
struct r82600_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
r82600_get_error_info(mci, &info);
r82600_process_error_info(mci, &info, 1);
}

6
drivers/edac/skx_base.c
View File

@ -174,7 +174,7 @@ static bool skx_check_ecc(u32 mcmtr)
return !!GET_BITFIELD(mcmtr, 2, 2);
}
static int skx_get_dimm_config(struct mem_ctl_info *mci)
static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg)
{
struct skx_pvt *pvt = mci->pvt_info;
u32 mtr, mcmtr, amap, mcddrtcfg;
@ -195,7 +195,7 @@ static int skx_get_dimm_config(struct mem_ctl_info *mci)
pci_read_config_dword(imc->chan[i].cdev,
0x80 + 4 * j, &mtr);
if (IS_DIMM_PRESENT(mtr)) {
ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j);
ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg);
} else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
EDAC_MOD_STR);
@ -702,7 +702,7 @@ static int __init skx_init(void)
d->imc[i].node_id = node_id;
rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
"Skylake Socket", EDAC_MOD_STR,
skx_get_dimm_config);
skx_get_dimm_config, cfg);
if (rc < 0)
goto fail;
}

23
drivers/edac/skx_common.c
View File

@ -304,15 +304,25 @@ static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
#define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
struct skx_imc *imc, int chan, int dimmno)
struct skx_imc *imc, int chan, int dimmno,
struct res_config *cfg)
{
int banks = 16, ranks, rows, cols, npages;
int banks, ranks, rows, cols, npages;
enum mem_type mtype;
u64 size;
ranks = numrank(mtr);
rows = numrow(mtr);
cols = numcol(mtr);
if (cfg->support_ddr5 && (amap & 0x8)) {
banks = 32;
mtype = MEM_DDR5;
} else {
banks = 16;
mtype = MEM_DDR4;
}
/*
* Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
*/
@ -332,7 +342,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
dimm->nr_pages = npages;
dimm->grain = 32;
dimm->dtype = get_width(mtr);
dimm->mtype = MEM_DDR4;
dimm->mtype = mtype;
dimm->edac_mode = EDAC_SECDED; /* likely better than this */
snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
imc->src_id, imc->lmc, chan, dimmno);
@ -390,7 +400,8 @@ unknown_size:
int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
const char *ctl_name, const char *mod_str,
get_dimm_config_f get_dimm_config)
get_dimm_config_f get_dimm_config,
struct res_config *cfg)
{
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2];
@ -425,13 +436,15 @@ int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
}
mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
if (cfg->support_ddr5)
mci->mtype_cap |= MEM_FLAG_DDR5;
mci->edac_ctl_cap = EDAC_FLAG_NONE;
mci->edac_cap = EDAC_FLAG_NONE;
mci->mod_name = mod_str;
mci->dev_name = pci_name(pdev);
mci->ctl_page_to_phys = NULL;
rc = get_dimm_config(mci);
rc = get_dimm_config(mci, cfg);
if (rc < 0)
goto fail;

16
drivers/edac/skx_common.h
View File

@ -59,6 +59,7 @@ struct skx_dev {
struct mem_ctl_info *mci;
struct pci_dev *mdev; /* for i10nm CPU */
void __iomem *mbase; /* for i10nm CPU */
int chan_mmio_sz; /* for i10nm CPU */
u8 mc; /* system wide mc# */
u8 lmc; /* socket relative mc# */
u8 src_id, node_id;
@ -82,7 +83,8 @@ struct skx_pvt {
enum type {
SKX,
I10NM
I10NM,
SPR
};
enum {
@ -118,9 +120,13 @@ struct res_config {
unsigned int decs_did;
/* Default bus number configuration register offset */
int busno_cfg_offset;
/* Per DDR channel memory-mapped I/O size */
int ddr_chan_mmio_sz;
bool support_ddr5;
};
typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci);
typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
struct res_config *cfg);
typedef bool (*skx_decode_f)(struct decoded_addr *res);
typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len);
@ -136,14 +142,16 @@ int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);
int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
struct skx_imc *imc, int chan, int dimmno);
struct skx_imc *imc, int chan, int dimmno,
struct res_config *cfg);
int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
int chan, int dimmno, const char *mod_str);
int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
const char *ctl_name, const char *mod_str,
get_dimm_config_f get_dimm_config);
get_dimm_config_f get_dimm_config,
struct res_config *cfg);
int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
void *data);

3
drivers/edac/synopsys_edac.c
View File

@ -1344,7 +1344,8 @@ static int mc_probe(struct platform_device *pdev)
#ifdef CONFIG_EDAC_DEBUG
if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
if (edac_create_sysfs_attributes(mci)) {
rc = edac_create_sysfs_attributes(mci);
if (rc) {
edac_printk(KERN_ERR, EDAC_MC,
"Failed to create sysfs entries\n");
goto free_edac_mc;

1
drivers/edac/x38_edac.c
View File

@ -238,7 +238,6 @@ static void x38_check(struct mem_ctl_info *mci)
{
struct x38_error_info info;
edac_dbg(1, "MC%d\n", mci->mc_idx);
x38_get_and_clear_error_info(mci, &info);
x38_process_error_info(mci, &info);
}

16
include/linux/edac.h
View File

@ -175,11 +175,15 @@ static inline char *mc_event_error_type(const unsigned int err_type)
* @MEM_RDDR3: Registered DDR3 RAM
* This is a variant of the DDR3 memories.
* @MEM_LRDDR3: Load-Reduced DDR3 memory.
* @MEM_LPDDR3: Low-Power DDR3 memory.
* @MEM_DDR4: Unbuffered DDR4 RAM
* @MEM_RDDR4: Registered DDR4 RAM
* This is a variant of the DDR4 memories.
* @MEM_LRDDR4: Load-Reduced DDR4 memory.
* @MEM_LPDDR4: Low-Power DDR4 memory.
* @MEM_DDR5: Unbuffered DDR5 RAM
* @MEM_NVDIMM: Non-volatile RAM
* @MEM_WIO2: Wide I/O 2.
*/
enum mem_type {
MEM_EMPTY = 0,
@ -200,10 +204,14 @@ enum mem_type {
MEM_DDR3,
MEM_RDDR3,
MEM_LRDDR3,
MEM_LPDDR3,
MEM_DDR4,
MEM_RDDR4,
MEM_LRDDR4,
MEM_LPDDR4,
MEM_DDR5,
MEM_NVDIMM,
MEM_WIO2,
};
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
@ -223,13 +231,17 @@ enum mem_type {
#define MEM_FLAG_XDR BIT(MEM_XDR)
#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
#define MEM_FLAG_LPDDR3 BIT(MEM_LPDDR3)
#define MEM_FLAG_DDR4 BIT(MEM_DDR4)
#define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
#define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
#define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4)
#define MEM_FLAG_DDR5 BIT(MEM_DDR5)
#define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
#define MEM_FLAG_WIO2 BIT(MEM_WIO2)
/**
* enum edac-type - Error Detection and Correction capabilities and mode
* enum edac_type - Error Detection and Correction capabilities and mode
* @EDAC_UNKNOWN: Unknown if ECC is available
* @EDAC_NONE: Doesn't support ECC
* @EDAC_RESERVED: Reserved ECC type
@ -309,7 +321,7 @@ enum scrub_type {
#define OP_OFFLINE 0x300
/**
* enum edac_mc_layer - memory controller hierarchy layer
* enum edac_mc_layer_type - memory controller hierarchy layer
*
* @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
* @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"