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arm64: dts: imx8m: assign clocks for A53 

Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and
assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what
is done in drivers/clk/imx/clk-imx8m*.c, then we could remove
the settings in driver which triggers lockdep warning.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Peng Fan 2020-05-07 13:56:10 +08:00 committed by Shawn Guo
parent a0a44420e5
commit 9e6337e6fd
4 changed files with 29 additions and 11 deletions
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10
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -519,16 +519,20 @@
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MM_CLK_NOC>,
assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
<&clk IMX8MM_CLK_A53_CORE>,
<&clk IMX8MM_CLK_NOC>,
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
<&clk IMX8MM_VIDEO_PLL1>,
<&clk IMX8MM_AUDIO_PLL1>,
<&clk IMX8MM_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
<&clk IMX8MM_ARM_PLL_OUT>,
<&clk IMX8MM_SYS_PLL3_OUT>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <0>,
assigned-clock-rates = <0>, <0>, <0>,
<400000000>,
<400000000>,
<750000000>,

10
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -426,13 +426,17 @@
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MN_CLK_NOC>,
assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
<&clk IMX8MN_CLK_A53_CORE>,
<&clk IMX8MN_CLK_NOC>,
<&clk IMX8MN_CLK_AUDIO_AHB>,
<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MN_SYS_PLL3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_ARM_PLL_OUT>,
<&clk IMX8MN_SYS_PLL3_OUT>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <0>,
assigned-clock-rates = <0>, <0>, <0>,
<400000000>,
<400000000>,
<600000000>;

11
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -360,7 +360,9 @@
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MP_CLK_NOC>,
assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
<&clk IMX8MP_CLK_NOC_IO>,
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
@ -368,12 +370,15 @@
<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_ARM_PLL_OUT>,
<&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <1000000000>,
assigned-clock-rates = <0>, <0>,
<1000000000>,
<800000000>,
<500000000>,
<400000000>,

9
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -595,8 +595,13 @@
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
assigned-clock-rates = <800000000>;
assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
<&clk IMX8MQ_CLK_A53_CORE>,
<&clk IMX8MQ_CLK_NOC>;
assigned-clock-rates = <0>, <0>,
<800000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_ARM_PLL_OUT>;
};
src: reset-controller@30390000 {