arm64: dts: imx8m: assign clocks for A53
Assign IMX8M*_CLK_A53_SRC's parent to system pll1 and assign IMX8M*_CLK_A53_CORE's parent to arm pll out as what is done in drivers/clk/imx/clk-imx8m*.c, then we could remove the settings in driver which triggers lockdep warning. Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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a0a44420e5
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@ -519,16 +519,20 @@
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<&clk_ext3>, <&clk_ext4>;
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<&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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"clk_ext3", "clk_ext4";
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"clk_ext3", "clk_ext4";
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assigned-clocks = <&clk IMX8MM_CLK_NOC>,
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assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
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<&clk IMX8MM_CLK_A53_CORE>,
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<&clk IMX8MM_CLK_NOC>,
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<&clk IMX8MM_CLK_AUDIO_AHB>,
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<&clk IMX8MM_CLK_AUDIO_AHB>,
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<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MM_SYS_PLL3>,
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<&clk IMX8MM_SYS_PLL3>,
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<&clk IMX8MM_VIDEO_PLL1>,
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<&clk IMX8MM_VIDEO_PLL1>,
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<&clk IMX8MM_AUDIO_PLL1>,
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<&clk IMX8MM_AUDIO_PLL1>,
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<&clk IMX8MM_AUDIO_PLL2>;
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<&clk IMX8MM_AUDIO_PLL2>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
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<&clk IMX8MM_ARM_PLL_OUT>,
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<&clk IMX8MM_SYS_PLL3_OUT>,
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<&clk IMX8MM_SYS_PLL1_800M>;
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<&clk IMX8MM_SYS_PLL1_800M>;
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assigned-clock-rates = <0>,
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assigned-clock-rates = <0>, <0>, <0>,
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<400000000>,
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<400000000>,
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<400000000>,
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<400000000>,
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<750000000>,
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<750000000>,
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@ -426,13 +426,17 @@
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<&clk_ext3>, <&clk_ext4>;
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<&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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"clk_ext3", "clk_ext4";
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"clk_ext3", "clk_ext4";
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assigned-clocks = <&clk IMX8MN_CLK_NOC>,
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assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
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<&clk IMX8MN_CLK_A53_CORE>,
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<&clk IMX8MN_CLK_NOC>,
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<&clk IMX8MN_CLK_AUDIO_AHB>,
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<&clk IMX8MN_CLK_AUDIO_AHB>,
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<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MN_SYS_PLL3>;
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<&clk IMX8MN_SYS_PLL3>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
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<&clk IMX8MN_ARM_PLL_OUT>,
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<&clk IMX8MN_SYS_PLL3_OUT>,
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<&clk IMX8MN_SYS_PLL1_800M>;
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<&clk IMX8MN_SYS_PLL1_800M>;
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assigned-clock-rates = <0>,
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assigned-clock-rates = <0>, <0>, <0>,
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<400000000>,
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<400000000>,
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<400000000>,
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<400000000>,
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<600000000>;
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<600000000>;
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@ -360,7 +360,9 @@
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<&clk_ext3>, <&clk_ext4>;
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<&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
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"clk_ext3", "clk_ext4";
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"clk_ext3", "clk_ext4";
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assigned-clocks = <&clk IMX8MP_CLK_NOC>,
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assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
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<&clk IMX8MP_CLK_A53_CORE>,
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<&clk IMX8MP_CLK_NOC>,
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<&clk IMX8MP_CLK_NOC_IO>,
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<&clk IMX8MP_CLK_NOC_IO>,
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<&clk IMX8MP_CLK_GIC>,
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<&clk IMX8MP_CLK_GIC>,
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<&clk IMX8MP_CLK_AUDIO_AHB>,
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<&clk IMX8MP_CLK_AUDIO_AHB>,
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@ -368,12 +370,15 @@
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<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
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<&clk IMX8MP_AUDIO_PLL1>,
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<&clk IMX8MP_AUDIO_PLL1>,
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<&clk IMX8MP_AUDIO_PLL2>;
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<&clk IMX8MP_AUDIO_PLL2>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_ARM_PLL_OUT>,
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<&clk IMX8MP_SYS_PLL2_1000M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL2_500M>,
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<&clk IMX8MP_SYS_PLL2_500M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>,
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<&clk IMX8MP_SYS_PLL1_800M>;
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<&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <1000000000>,
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assigned-clock-rates = <0>, <0>,
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<1000000000>,
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<800000000>,
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<800000000>,
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<500000000>,
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<500000000>,
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<400000000>,
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<400000000>,
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@ -595,8 +595,13 @@
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clock-names = "ckil", "osc_25m", "osc_27m",
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clock-names = "ckil", "osc_25m", "osc_27m",
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"clk_ext1", "clk_ext2",
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"clk_ext1", "clk_ext2",
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"clk_ext3", "clk_ext4";
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"clk_ext3", "clk_ext4";
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assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
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assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
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assigned-clock-rates = <800000000>;
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<&clk IMX8MQ_CLK_A53_CORE>,
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<&clk IMX8MQ_CLK_NOC>;
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assigned-clock-rates = <0>, <0>,
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<800000000>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
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<&clk IMX8MQ_ARM_PLL_OUT>;
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};
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};
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src: reset-controller@30390000 {
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src: reset-controller@30390000 {
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