drm/amdgpu/soc15: add clock gating functions for raven
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -819,6 +819,20 @@ static int soc15_common_set_clockgating_state(void *handle,
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soc15_update_df_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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break;
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case CHIP_RAVEN:
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nbio_v6_1_update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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nbio_v6_1_update_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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soc15_update_hdp_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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soc15_update_drm_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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soc15_update_drm_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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soc15_update_rom_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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break;
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default:
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break;
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}
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