From ec6bd78a09d9967c4fcec53e7fabfaabd4f0e367 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 8 Feb 2017 15:37:47 -0600 Subject: [PATCH 1/2] PCI: xilinx: Configure PCIe MPS settings Make sure PCIe MPS settings are valid when we enumerate a new hierarchy. Based-on-patch-by: Jon Mason Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-xilinx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index c8616fadccf1..7f030f5d750b 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -632,7 +632,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct xilinx_pcie_port *port; - struct pci_bus *bus; + struct pci_bus *bus, *child; int err; resource_size_t iobase = 0; LIST_HEAD(res); @@ -686,6 +686,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #ifndef CONFIG_MICROBLAZE pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); #endif + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); pci_bus_add_devices(bus); return 0; From 26b54be568ad8611ebc62f02f9a5d5328e7b3392 Mon Sep 17 00:00:00 2001 From: Bharat Kumar Gogada Date: Tue, 31 Jan 2017 14:29:30 +0530 Subject: [PATCH 2/2] PCI: xilinx-nwl: Remove mask for messages not supported by AXI Remove support for vendor-defined messages which are not supported by AXI. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-xilinx-nwl.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index 43eaa4afab94..4c3e0ab35496 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -62,21 +62,9 @@ #define CFG_ENABLE_PM_MSG_FWD BIT(1) #define CFG_ENABLE_INT_MSG_FWD BIT(2) #define CFG_ENABLE_ERR_MSG_FWD BIT(3) -#define CFG_ENABLE_SLT_MSG_FWD BIT(5) -#define CFG_ENABLE_VEN_MSG_FWD BIT(7) -#define CFG_ENABLE_OTH_MSG_FWD BIT(13) -#define CFG_ENABLE_VEN_MSG_EN BIT(14) -#define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15) -#define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16) #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ CFG_ENABLE_INT_MSG_FWD | \ - CFG_ENABLE_ERR_MSG_FWD | \ - CFG_ENABLE_SLT_MSG_FWD | \ - CFG_ENABLE_VEN_MSG_FWD | \ - CFG_ENABLE_OTH_MSG_FWD | \ - CFG_ENABLE_VEN_MSG_EN | \ - CFG_ENABLE_VEN_MSG_VEN_INV | \ - CFG_ENABLE_VEN_MSG_VEN_ID) + CFG_ENABLE_ERR_MSG_FWD) /* Misc interrupt status mask bits */ #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)