arm: zynq: Do not use xilinx specific function names
Remove all xilinx specific names from the driver because this is generic driver for cadence ttc. xttc->ttc ttcps->ttc ... No functional changes in this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
parent
c5263bb8b7
commit
9e09dc5f7f
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@ -1,5 +1,5 @@
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/*
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* This file contains driver for the Xilinx PS Timer Counter IP.
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* This file contains driver for the Cadence Triple Timer Counter Rev 06
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*
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* Copyright (C) 2011-2013 Xilinx
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*
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@ -42,14 +42,14 @@
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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*/
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1
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#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
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/*
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* Setup the timers to use pre-scaling, using a fixed value for now that will
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@ -62,161 +62,161 @@
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#define CNT_CNTRL_RESET (1 << 4)
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/**
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* struct xttcps_timer - This definition defines local timer structure
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* struct ttc_timer - This definition defines local timer structure
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*
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* @base_addr: Base address of timer
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* @clk: Associated clock source
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* @clk_rate_change_nb Notifier block for clock rate changes
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*/
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struct xttcps_timer {
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struct ttc_timer {
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void __iomem *base_addr;
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struct clk *clk;
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struct notifier_block clk_rate_change_nb;
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};
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#define to_xttcps_timer(x) \
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container_of(x, struct xttcps_timer, clk_rate_change_nb)
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#define to_ttc_timer(x) \
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container_of(x, struct ttc_timer, clk_rate_change_nb)
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struct xttcps_timer_clocksource {
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struct xttcps_timer xttc;
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struct ttc_timer_clocksource {
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struct ttc_timer ttc;
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struct clocksource cs;
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};
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#define to_xttcps_timer_clksrc(x) \
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container_of(x, struct xttcps_timer_clocksource, cs)
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#define to_ttc_timer_clksrc(x) \
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container_of(x, struct ttc_timer_clocksource, cs)
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struct xttcps_timer_clockevent {
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struct xttcps_timer xttc;
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struct ttc_timer_clockevent {
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struct ttc_timer ttc;
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struct clock_event_device ce;
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};
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#define to_xttcps_timer_clkevent(x) \
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container_of(x, struct xttcps_timer_clockevent, ce)
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#define to_ttc_timer_clkevent(x) \
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container_of(x, struct ttc_timer_clockevent, ce)
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/**
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* xttcps_set_interval - Set the timer interval value
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* ttc_set_interval - Set the timer interval value
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*
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* @timer: Pointer to the timer instance
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* @cycles: Timer interval ticks
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**/
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static void xttcps_set_interval(struct xttcps_timer *timer,
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static void ttc_set_interval(struct ttc_timer *timer,
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unsigned long cycles)
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{
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
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__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
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/*
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* Reset the counter (0x10) so that it starts from 0, one-shot
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* mode makes this needed for timing to be right.
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*/
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ctrl_reg |= CNT_CNTRL_RESET;
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ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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}
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/**
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* xttcps_clock_event_interrupt - Clock event timer interrupt handler
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* ttc_clock_event_interrupt - Clock event timer interrupt handler
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*
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* @irq: IRQ number of the Timer
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* @dev_id: void pointer to the xttcps_timer instance
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* @dev_id: void pointer to the ttc_timer instance
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*
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* returns: Always IRQ_HANDLED - success
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**/
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static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
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static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
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{
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struct xttcps_timer_clockevent *xttce = dev_id;
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struct xttcps_timer *timer = &xttce->xttc;
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struct ttc_timer_clockevent *ttce = dev_id;
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struct ttc_timer *timer = &ttce->ttc;
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/* Acknowledge the interrupt and call event handler */
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__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
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__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
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xttce->ce.event_handler(&xttce->ce);
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ttce->ce.event_handler(&ttce->ce);
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return IRQ_HANDLED;
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}
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/**
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* __xttc_clocksource_read - Reads the timer counter register
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* __ttc_clocksource_read - Reads the timer counter register
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*
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* returns: Current timer counter register value
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**/
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static cycle_t __xttc_clocksource_read(struct clocksource *cs)
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static cycle_t __ttc_clocksource_read(struct clocksource *cs)
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{
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struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
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struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
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return (cycle_t)__raw_readl(timer->base_addr +
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XTTCPS_COUNT_VAL_OFFSET);
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TTC_COUNT_VAL_OFFSET);
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}
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/**
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* xttcps_set_next_event - Sets the time interval for next event
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* ttc_set_next_event - Sets the time interval for next event
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*
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* @cycles: Timer interval ticks
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* @evt: Address of clock event instance
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*
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* returns: Always 0 - success
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**/
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static int xttcps_set_next_event(unsigned long cycles,
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static int ttc_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
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struct xttcps_timer *timer = &xttce->xttc;
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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xttcps_set_interval(timer, cycles);
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ttc_set_interval(timer, cycles);
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return 0;
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}
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/**
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* xttcps_set_mode - Sets the mode of timer
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* ttc_set_mode - Sets the mode of timer
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*
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* @mode: Mode to be set
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* @evt: Address of clock event instance
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**/
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static void xttcps_set_mode(enum clock_event_mode mode,
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static void ttc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
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struct xttcps_timer *timer = &xttce->xttc;
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struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
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struct ttc_timer *timer = &ttce->ttc;
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u32 ctrl_reg;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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xttcps_set_interval(timer,
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DIV_ROUND_CLOSEST(clk_get_rate(xttce->xttc.clk),
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ttc_set_interval(timer,
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DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
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PRESCALE * HZ));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl_reg = __raw_readl(timer->base_addr +
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XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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case CLOCK_EVT_MODE_RESUME:
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ctrl_reg = __raw_readl(timer->base_addr +
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XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
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TTC_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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timer->base_addr + TTC_CNT_CNTRL_OFFSET);
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break;
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}
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}
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static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb,
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static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct xttcps_timer *xttcps = to_xttcps_timer(nb);
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struct xttcps_timer_clocksource *xttccs = container_of(xttcps,
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struct xttcps_timer_clocksource, xttc);
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struct ttc_timer *ttc = to_ttc_timer(nb);
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struct ttc_timer_clocksource *ttccs = container_of(ttc,
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struct ttc_timer_clocksource, ttc);
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switch (event) {
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case POST_RATE_CHANGE:
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@ -236,8 +236,8 @@ static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb,
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* one unregister call, but only trigger one clocksource switch
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* for the cost of another HW timer used by the OS.
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*/
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clocksource_unregister(&xttccs->cs);
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clocksource_register_hz(&xttccs->cs,
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clocksource_unregister(&ttccs->cs);
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clocksource_register_hz(&ttccs->cs,
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ndata->new_rate / PRESCALE);
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/* fall through */
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case PRE_RATE_CHANGE:
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@ -247,34 +247,34 @@ static int xttcps_rate_change_clocksource_cb(struct notifier_block *nb,
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}
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}
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static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base)
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static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
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{
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struct xttcps_timer_clocksource *ttccs;
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struct ttc_timer_clocksource *ttccs;
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int err;
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ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
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if (WARN_ON(!ttccs))
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return;
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ttccs->xttc.clk = clk;
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ttccs->ttc.clk = clk;
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err = clk_prepare_enable(ttccs->xttc.clk);
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err = clk_prepare_enable(ttccs->ttc.clk);
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if (WARN_ON(err)) {
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kfree(ttccs);
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return;
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}
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ttccs->xttc.clk_rate_change_nb.notifier_call =
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xttcps_rate_change_clocksource_cb;
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ttccs->xttc.clk_rate_change_nb.next = NULL;
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if (clk_notifier_register(ttccs->xttc.clk,
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&ttccs->xttc.clk_rate_change_nb))
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ttccs->ttc.clk_rate_change_nb.notifier_call =
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ttc_rate_change_clocksource_cb;
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ttccs->ttc.clk_rate_change_nb.next = NULL;
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if (clk_notifier_register(ttccs->ttc.clk,
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&ttccs->ttc.clk_rate_change_nb))
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pr_warn("Unable to register clock notifier.\n");
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ttccs->xttc.base_addr = base;
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ttccs->cs.name = "xttcps_clocksource";
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ttccs->ttc.base_addr = base;
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ttccs->cs.name = "ttc_clocksource";
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ttccs->cs.rating = 200;
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ttccs->cs.read = __xttc_clocksource_read;
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ttccs->cs.read = __ttc_clocksource_read;
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ttccs->cs.mask = CLOCKSOURCE_MASK(16);
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ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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@ -283,27 +283,27 @@ static void __init xttc_setup_clocksource(struct clk *clk, void __iomem *base)
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
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* it by 32 also. Let it start running now.
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*/
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__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
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__raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
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ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
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__raw_writel(CNT_CNTRL_RESET,
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ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
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err = clocksource_register_hz(&ttccs->cs,
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clk_get_rate(ttccs->xttc.clk) / PRESCALE);
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clk_get_rate(ttccs->ttc.clk) / PRESCALE);
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if (WARN_ON(err)) {
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kfree(ttccs);
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return;
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}
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}
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static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb,
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static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct xttcps_timer *xttcps = to_xttcps_timer(nb);
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struct xttcps_timer_clockevent *xttcce = container_of(xttcps,
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struct xttcps_timer_clockevent, xttc);
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struct ttc_timer *ttc = to_ttc_timer(nb);
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struct ttc_timer_clockevent *ttcce = container_of(ttc,
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struct ttc_timer_clockevent, ttc);
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switch (event) {
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case POST_RATE_CHANGE:
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@ -317,7 +317,7 @@ static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb,
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* cores.
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*/
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local_irq_save(flags);
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clockevents_update_freq(&xttcce->ce,
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clockevents_update_freq(&ttcce->ce,
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ndata->new_rate / PRESCALE);
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local_irq_restore(flags);
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@ -330,36 +330,36 @@ static int xttcps_rate_change_clockevent_cb(struct notifier_block *nb,
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}
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}
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static void __init xttc_setup_clockevent(struct clk *clk,
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static void __init ttc_setup_clockevent(struct clk *clk,
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void __iomem *base, u32 irq)
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{
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struct xttcps_timer_clockevent *ttcce;
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struct ttc_timer_clockevent *ttcce;
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int err;
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ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
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if (WARN_ON(!ttcce))
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return;
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ttcce->xttc.clk = clk;
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ttcce->ttc.clk = clk;
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err = clk_prepare_enable(ttcce->xttc.clk);
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err = clk_prepare_enable(ttcce->ttc.clk);
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if (WARN_ON(err)) {
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kfree(ttcce);
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return;
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}
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ttcce->xttc.clk_rate_change_nb.notifier_call =
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xttcps_rate_change_clockevent_cb;
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ttcce->xttc.clk_rate_change_nb.next = NULL;
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if (clk_notifier_register(ttcce->xttc.clk,
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&ttcce->xttc.clk_rate_change_nb))
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ttcce->ttc.clk_rate_change_nb.notifier_call =
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ttc_rate_change_clockevent_cb;
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ttcce->ttc.clk_rate_change_nb.next = NULL;
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if (clk_notifier_register(ttcce->ttc.clk,
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&ttcce->ttc.clk_rate_change_nb))
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pr_warn("Unable to register clock notifier.\n");
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ttcce->xttc.base_addr = base;
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ttcce->ce.name = "xttcps_clockevent";
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ttcce->ttc.base_addr = base;
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ttcce->ce.name = "ttc_clockevent";
|
||||
ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
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ttcce->ce.set_next_event = xttcps_set_next_event;
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||||
ttcce->ce.set_mode = xttcps_set_mode;
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ttcce->ce.set_next_event = ttc_set_next_event;
|
||||
ttcce->ce.set_mode = ttc_set_mode;
|
||||
ttcce->ce.rating = 200;
|
||||
ttcce->ce.irq = irq;
|
||||
ttcce->ce.cpumask = cpu_possible_mask;
|
||||
|
|
@ -369,12 +369,12 @@ static void __init xttc_setup_clockevent(struct clk *clk,
|
|||
* is prescaled by 32 using the interval interrupt. Leave it
|
||||
* disabled for now.
|
||||
*/
|
||||
__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
|
||||
__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
|
||||
__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
|
||||
ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
|
||||
__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
|
||||
ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
|
||||
__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
|
||||
|
||||
err = request_irq(irq, xttcps_clock_event_interrupt,
|
||||
err = request_irq(irq, ttc_clock_event_interrupt,
|
||||
IRQF_DISABLED | IRQF_TIMER,
|
||||
ttcce->ce.name, ttcce);
|
||||
if (WARN_ON(err)) {
|
||||
|
|
@ -383,16 +383,16 @@ static void __init xttc_setup_clockevent(struct clk *clk,
|
|||
}
|
||||
|
||||
clockevents_config_and_register(&ttcce->ce,
|
||||
clk_get_rate(ttcce->xttc.clk) / PRESCALE, 1, 0xfffe);
|
||||
clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
|
||||
}
|
||||
|
||||
/**
|
||||
* xttcps_timer_init - Initialize the timer
|
||||
* ttc_timer_init - Initialize the timer
|
||||
*
|
||||
* Initializes the timer hardware and register the clock source and clock event
|
||||
* timers with Linux kernal timer framework
|
||||
*/
|
||||
static void __init xttcps_timer_init(struct device_node *timer)
|
||||
static void __init ttc_timer_init(struct device_node *timer)
|
||||
{
|
||||
unsigned int irq;
|
||||
void __iomem *timer_baseaddr;
|
||||
|
|
@ -427,10 +427,10 @@ static void __init xttcps_timer_init(struct device_node *timer)
|
|||
BUG();
|
||||
}
|
||||
|
||||
xttc_setup_clocksource(clk, timer_baseaddr);
|
||||
xttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
|
||||
ttc_setup_clocksource(clk, timer_baseaddr);
|
||||
ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
|
||||
|
||||
pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
|
||||
}
|
||||
|
||||
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", xttcps_timer_init);
|
||||
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
|
||||
|
|
|
|||
Loading…
Reference in New Issue