mtd: pxa3xx_nand: set oob length in the runtime
For different command need different oob requirement, set the proper oob length by different cmd. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -273,13 +273,20 @@ static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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/* calculate data size */
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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info->data_size = info->page_size;
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if (!oob_enable) {
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info->oob_size = 0;
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return;
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}
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switch (info->page_size) {
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case 2048:
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info->data_size = (info->use_ecc) ? 2088 : 2112;
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info->oob_size = (info->use_ecc) ? 40 : 64;
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break;
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case 512:
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info->data_size = (info->use_ecc) ? 520 : 528;
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info->oob_size = (info->use_ecc) ? 8 : 16;
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break;
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}
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}
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@ -333,6 +340,7 @@ static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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info->oob_size = 0;
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if (cmd == cmdset->read_id) {
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info->ndcb0 |= NDCB0_CMD_TYPE(3);
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info->data_size = 8;
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@ -401,6 +409,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
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case STATE_PIO_WRITING:
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__raw_writesl(info->mmio_base + NDDB, info->data_buff,
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DIV_ROUND_UP(info->data_size, 4));
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if (info->oob_size > 0)
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__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
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DIV_ROUND_UP(info->oob_size, 4));
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enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
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@ -413,6 +424,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
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case STATE_PIO_READING:
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__raw_readsl(info->mmio_base + NDDB, info->data_buff,
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DIV_ROUND_UP(info->data_size, 4));
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if (info->oob_size > 0)
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__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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default:
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printk(KERN_ERR "%s: invalid state %d\n", __func__,
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@ -427,7 +441,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
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static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
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{
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struct pxa_dma_desc *desc = info->data_desc;
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int dma_len = ALIGN(info->data_size, 32);
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int dma_len = ALIGN(info->data_size + info->oob_size, 32);
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desc->ddadr = DDADR_STOP;
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desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
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@ -833,7 +847,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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info->cmdset = f->cmdset;
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info->page_size = f->page_size;
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info->oob_buff = info->data_buff + f->page_size;
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info->oob_size = (f->page_size == 2048) ? 64 : 16;
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info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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/* calculate addressing information */
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@ -892,8 +905,6 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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i = __ffs(page_per_block * info->page_size);
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num_blocks = type->chipsize << (20 - i);
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info->oob_size = (info->page_size == 2048) ? 64 : 16;
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/* calculate addressing information */
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info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
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