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drm/amdgpu: add vram_info v2_5 in atomfirmware header 

vram_info v2_5 was introduced to support sienna_cichlid

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2020-01-20 04:41:40 +08:00 committed by Alex Deucher
parent f95c20464d
commit 9d3708169f
1 changed files with 124 additions and 0 deletions
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124
drivers/gpu/drm/amd/include/atomfirmware.h
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@ -2313,6 +2313,130 @@ struct atom_vram_info_header_v2_4 {
struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
};
struct atom_vram_module_v11 {
// Design Specific Values
uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
uint16_t mem_voltage; // mem_voltage
uint16_t vram_module_size; // Size of atom_vram_module_v9
uint8_t ext_memory_id; // Current memory module ID
uint8_t memory_type; // enum of atom_dgpu_vram_type
uint8_t channel_num; // Number of mem. channels supported in this module
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
uint8_t tunningset_id; // MC phy registers set per.
uint16_t reserved[4]; // reserved
uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
uint8_t vram_flags; // bit0= bankgroup enable
uint8_t vram_rsd2; // reserved
uint16_t gddr6_mr10; // gddr6 mode register10 value
uint16_t gddr6_mr0; // gddr6 mode register0 value
uint16_t gddr6_mr1; // gddr6 mode register1 value
uint16_t gddr6_mr2; // gddr6 mode register2 value
uint16_t gddr6_mr4; // gddr6 mode register4 value
uint16_t gddr6_mr7; // gddr6 mode register7 value
uint16_t gddr6_mr8; // gddr6 mode register8 value
char dram_pnstring[40]; // part number end with '0'.
};
struct atom_gddr6_ac_timing_v2_5 {
uint32_t u32umc_id_access;
uint8_t RL;
uint8_t WL;
uint8_t tRAS;
uint8_t tRC;
uint16_t tREFI;
uint8_t tRFC;
uint8_t tRFCpb;
uint8_t tRREFD;
uint8_t tRCDRD;
uint8_t tRCDWR;
uint8_t tRP;
uint8_t tRRDS;
uint8_t tRRDL;
uint8_t tWR;
uint8_t tWTRS;
uint8_t tWTRL;
uint8_t tFAW;
uint8_t tCCDS;
uint8_t tCCDL;
uint8_t tCRCRL;
uint8_t tCRCWL;
uint8_t tCKE;
uint8_t tCKSRE;
uint8_t tCKSRX;
uint8_t tRTPS;
uint8_t tRTPL;
uint8_t tMRD;
uint8_t tMOD;
uint8_t tXS;
uint8_t tXHP;
uint8_t tXSMRS;
uint32_t tXSH;
uint8_t tPD;
uint8_t tXP;
uint8_t tCPDED;
uint8_t tACTPDE;
uint8_t tPREPDE;
uint8_t tREFPDE;
uint8_t tMRSPDEN;
uint8_t tRDSRE;
uint8_t tWRSRE;
uint8_t tPPD;
uint8_t tCCDMW;
uint8_t tWTRTR;
uint8_t tLTLTR;
uint8_t tREFTR;
uint8_t VNDR;
uint8_t reserved[9];
};
struct atom_gddr6_bit_byte_remap {
uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap
uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0
uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1
uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2
uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0
uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1
uint32_t phy_dram; //mmUMC_PHY_DRAM
};
struct atom_gddr6_dram_data_remap {
uint32_t table_size;
uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
};
struct atom_vram_info_header_v2_5 {
struct atom_common_table_header table_header;
uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
uint16_t reserved; // offset of reserved
uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
uint8_t vram_module_num; // indicate number of VRAM module
uint8_t umcip_min_ver;
uint8_t umcip_max_ver;
uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
};
/*
***************************************************************************
Data Table voltageobject_info structure