Tesla FSD ARM64 changes for v5.18
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry and defconfig change. This brings and enables this new platform. This includes clock controller bindings (header files with clock IDs) which are shared also with Tesla FSD SoC clock controller pull request. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH9SB0QHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD1zpnD/9xV+X85LiKRWWuYeDtLBOzwuqCKAEVBX+U ZVGEuS675Ha4RrskEOWHBqxBePV7dposFaBWv59wGlnTESrz4N5jtdQu8WJYatp0 WzTTpgdmQBldKHjS1xtEBK7aZ3UOfvGEEGh+dkIX8U+DxdSzfil10XpnLeplOLUs pzpb8YdwSKX4VwRTRNuZpthN/VKTcIykANvm+DbKEl8F5kFjHWrlPFgU11XmLzZp ngzB2AeNHWqSjDJR/JZjbjlF7SsFCbfVTYBVLVoiiHKDVgpds6rM1LiR9OjY9skp W8egM8q2tO7mVNdFnNEK1k/CaioJUgBhEFUdxycR8Q0YoJP2dRnvQ3kEEI30suGY EoNULUyLLa61yMIgzQ8RF8RBo/Pb9lJDvr4DyG8InDANr9Y9bLHqi4Rmm4h6BJYb Y5cEhorY8qCmxBvllj9PdjCO0e1FanxO+RsVBgzDw3iBo6mrGXdFy1CppZ3BUSI1 NcNc5D5TRIkSo8JU9gFe+bVCjI2h1QQkZFERraH2f801wKQi7kD7/c8TE2KQR6Ej uz7BRA9cIlE2tDqzWVtmSM+ida5c8CsTGknk1aWKM6cwGB5wM6JhHnJfg4mBUGZj BCdUmRfqRYX4+2E01YyUjbqjbSGxYkvyPPw9LBr2ii3di4G7FInwfyrvD4O7IBBL UUn0MFjD3w== =tXfh -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY47wACgkQmmx57+YA GNnklg/8CNnZyxSIOo258Bixbpf7ArNIVXuwd2mDUQO5w/dt6/y1HPErk1x/FJO5 u4x3ugyCOJOPXnZy/We38M1NXJI7+RWfkvnHObGGLqsHf6YPICEUZqAlVuAT0fJn eWGTD1XOmf3m7r6xpSn8W6dxZ31tU/ST3WcecSBEcX4URJULdtF5Umqyh7RXTjYL HX3QvJwKxeNCnIUbsPJK7Iq0Y77AFgzPpn7iSO4qiP5lAK+YWRuT8jQKaIOGKJxz lw5rkYhq8pQD0Amlm/DYxrvfJJZEU83FEzMxx9ZmeeU3LoixVvWgA2H0phjZP03k 0sbshjOhUSLFIfduk1oZSbkYxQAsDsF8r1Jvrbr5LrVI+2C7vQoqTwG+neaqksnp CmNYDvAhugdVGHBGZTeQzeVMq8swV5o+3DJtlnKPp6gXlrJjFOECE63F4f1Pc+Fi CE9KRBLqFSrdHyAfi3bwAcS8tTnhRYx6I6NYjCp+qa4wEREw8X8HBLDRemWsoqB2 T19W864mkGPPbkmxaf5/F9LcJNU8tSd86E3hSIn1fgusEKTkv50KaEZ0GrLV45ou GYTAYfIVRG+9RZpQOlmHPMAJ2DIoHB1EXrvPmD73Tyrgo3sZhftClNkikZKbDGDp XplUjSnClvsUBe4cbO4zVw/s7wQwIe8x+CEl/3Ry2L6MV/fysMY= =l8Oq -----END PGP SIGNATURE----- Merge tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Tesla FSD ARM64 changes for v5.18 Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry and defconfig change. This brings and enables this new platform. This includes clock controller bindings (header files with clock IDs) which are shared also with Tesla FSD SoC clock controller pull request. * tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: fsd: Add SPI device nodes arm64: defconfig: Enable Tesla FSD SoC arm64: dts: fsd: Add initial pinctrl support arm64: dts: fsd: Add initial device tree support dt-bindings: clock: Document FSD CMU bindings dt-bindings: clock: Add bindings definitions for FSD CMU blocks dt-bindings: arm: add Tesla FSD ARM SoC dt-bindings: add vendor prefix for Tesla Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9d28fe1bec
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@ -0,0 +1,27 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/tesla.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tesla Full Self Driving(FSD) platforms device tree bindings
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maintainers:
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- Alim Akhtar <alim.akhtar@samsung.com>
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- linux-fsd@tesla.com
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: FSD SoC board
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items:
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- enum:
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- tesla,fsd-evb # Tesla FSD Evaluation
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- const: tesla,fsd
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additionalProperties: true
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...
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@ -0,0 +1,198 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tesla FSD (Full Self-Driving) SoC clock controller
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maintainers:
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- Alim Akhtar <alim.akhtar@samsung.com>
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- linux-fsd@tesla.com
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description: |
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FSD clock controller consist of several clock management unit
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(CMU), which generates clocks for various inteernal SoC blocks.
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The root clock comes from external OSC clock (24 MHz).
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All available clocks are defined as preprocessor macros in
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'dt-bindings/clock/fsd-clk.h' header.
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properties:
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compatible:
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enum:
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- tesla,fsd-clock-cmu
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- tesla,fsd-clock-imem
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- tesla,fsd-clock-peric
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- tesla,fsd-clock-fsys0
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- tesla,fsd-clock-fsys1
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- tesla,fsd-clock-mfc
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- tesla,fsd-clock-cam_csi
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clocks:
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minItems: 1
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maxItems: 6
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clock-names:
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minItems: 1
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maxItems: 6
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: tesla,fsd-clock-cmu
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24 MHz)
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clock-names:
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items:
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- const: fin_pll
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- if:
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properties:
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compatible:
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contains:
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const: tesla,fsd-clock-imem
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (24 MHz)
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- description: IMEM TCU clock (from CMU_CMU)
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- description: IMEM bus clock (from CMU_CMU)
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- description: IMEM DMA clock (from CMU_CMU)
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clock-names:
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items:
|
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- const: fin_pll
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- const: dout_cmu_imem_tcuclk
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- const: dout_cmu_imem_aclk
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- const: dout_cmu_imem_dmaclk
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|
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- if:
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properties:
|
||||
compatible:
|
||||
contains:
|
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const: tesla,fsd-clock-peric
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then:
|
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properties:
|
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clocks:
|
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items:
|
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- description: External reference clock (24 MHz)
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- description: Shared0 PLL div4 clock (from CMU_CMU)
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- description: PERIC shared1 div36 clock (from CMU_CMU)
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- description: PERIC shared0 div3 TBU clock (from CMU_CMU)
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- description: PERIC shared0 div20 clock (from CMU_CMU)
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- description: PERIC shared1 div4 DMAclock (from CMU_CMU)
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clock-names:
|
||||
items:
|
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- const: fin_pll
|
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- const: dout_cmu_pll_shared0_div4
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- const: dout_cmu_peric_shared1div36
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- const: dout_cmu_peric_shared0div3_tbuclk
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- const: dout_cmu_peric_shared0div20
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||||
- const: dout_cmu_peric_shared1div4_dmaclk
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||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys0
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then:
|
||||
properties:
|
||||
clocks:
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items:
|
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- description: External reference clock (24 MHz)
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- description: Shared0 PLL div6 clock (from CMU_CMU)
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- description: FSYS0 shared1 div4 clock (from CMU_CMU)
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||||
- description: FSYS0 shared0 div4 clock (from CMU_CMU)
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clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_pll_shared0_div6
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- const: dout_cmu_fsys0_shared1div4
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- const: dout_cmu_fsys0_shared0div4
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||||
|
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- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys1
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||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
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||||
- description: External reference clock (24 MHz)
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- description: FSYS1 shared0 div8 clock (from CMU_CMU)
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- description: FSYS1 shared0 div4 clock (from CMU_CMU)
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||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
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- const: dout_cmu_fsys1_shared0div8
|
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- const: dout_cmu_fsys1_shared0div4
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||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-mfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
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||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-cam_csi
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||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
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||||
|
||||
required:
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||||
- compatible
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||||
- "#clock-cells"
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||||
- clocks
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||||
- clock-names
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||||
- reg
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||||
|
||||
additionalProperties: false
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|
||||
examples:
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# Clock controller node for CMU_FSYS1
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- |
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#include <dt-bindings/clock/fsd-clk.h>
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clock_fsys1: clock-controller@16810000 {
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compatible = "tesla,fsd-clock-fsys1";
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reg = <0x16810000 0x3000>;
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#clock-cells = <1>;
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clocks = <&fin_pll>,
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<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
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<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
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clock-names = "fin_pll",
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"dout_cmu_fsys1_shared0div8",
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"dout_cmu_fsys1_shared0div4";
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};
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|
||||
...
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|
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@ -1205,6 +1205,8 @@ patternProperties:
|
|||
description: Shenzhen Techstar Electronics Co., Ltd.
|
||||
"^terasic,.*":
|
||||
description: Terasic Inc.
|
||||
"^tesla,.*":
|
||||
description: Tesla, Inc.
|
||||
"^tfc,.*":
|
||||
description: Three Five Corp
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||||
"^thead,.*":
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||||
|
|
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|
|
@ -2754,6 +2754,14 @@ S: Maintained
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|||
F: Documentation/devicetree/bindings/media/tegra-cec.txt
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F: drivers/media/cec/platform/tegra/
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ARM/TESLA FSD SoC SUPPORT
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M: Alim Akhtar <alim.akhtar@samsung.com>
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M: linux-fsd@tesla.com
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-samsung-soc@vger.kernel.org
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S: Maintained
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F: arch/arm64/boot/dts/tesla*
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ARM/TETON BGA MACHINE SUPPORT
|
||||
M: "Mark F. Brown" <mark.brown314@gmail.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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|
|
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@ -268,6 +268,12 @@ config ARCH_TEGRA
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_TESLA_FSD
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bool "ARMv8 based Tesla platform"
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depends on ARCH_EXYNOS
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help
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Support for ARMv8 based Tesla platforms.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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|
|
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@ -27,6 +27,7 @@ subdir-y += rockchip
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subdir-y += socionext
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subdir-y += sprd
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subdir-y += synaptics
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subdir-y += tesla
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subdir-y += ti
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subdir-y += toshiba
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subdir-y += xilinx
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|
|
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@ -0,0 +1,3 @@
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|||
# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_TESLA_FSD) += \
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fsd-evb.dtb
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|
@ -0,0 +1,39 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Tesla FSD board device tree source
|
||||
*
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* Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
|
||||
* Copyright (c) 2017-2021 Tesla, Inc.
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||||
* https://www.tesla.com
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||||
*/
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||||
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||||
/dts-v1/;
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#include "fsd.dtsi"
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/ {
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model = "Tesla Full Self-Driving (FSD) Evaluation board";
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compatible = "tesla,fsd-evb", "tesla,fsd";
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aliases {
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||||
serial0 = &serial_0;
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||||
serial1 = &serial_1;
|
||||
};
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chosen {
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stdout-path = &serial_0;
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||||
};
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||||
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||||
memory@80000000 {
|
||||
device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x00000000>;
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||||
};
|
||||
};
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||||
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&fin_pll {
|
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clock-frequency = <24000000>;
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||||
};
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|
||||
&serial_0 {
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||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
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||||
/*
|
||||
* Tesla Full Self-Driving SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
|
||||
* https://www.samsung.com
|
||||
* Copyright (c) 2017-2021 Tesla, Inc.
|
||||
* https://www.tesla.com
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
|
||||
&pinctrl_fsys0 {
|
||||
gpf0: gpf0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf1: gpf1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf6: gpf6-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf4: gpf4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf5: gpf5-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_peric {
|
||||
gpc8: gpc8-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf2: gpf2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpf3: gpf3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd0: gpd0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb0: gpb0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb1: gpb1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb4: gpb4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb5: gpb5-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb6: gpb6-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpb7: gpb7-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd1: gpd1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd2: gpd2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpd3: gpd3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg0: gpg0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg1: gpg1-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg2: gpg2-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg3: gpg3-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg4: gpg4-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg5: gpg5-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg6: gpg6-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpg7: gpg7-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pwm0_out: pwm0-out-pins {
|
||||
samsung,pins = "gpb6-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out-pins {
|
||||
samsung,pins = "gpb6-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
hs_i2c0_bus: hs-i2c0-bus-pins {
|
||||
samsung,pins = "gpb0-0", "gpb0-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c1_bus: hs-i2c1-bus-pins {
|
||||
samsung,pins = "gpb0-2", "gpb0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c2_bus: hs-i2c2-bus-pins {
|
||||
samsung,pins = "gpb0-4", "gpb0-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c3_bus: hs-i2c3-bus-pins {
|
||||
samsung,pins = "gpb0-6", "gpb0-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c4_bus: hs-i2c4-bus-pins {
|
||||
samsung,pins = "gpb1-0", "gpb1-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c5_bus: hs-i2c5-bus-pins {
|
||||
samsung,pins = "gpb1-2", "gpb1-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c6_bus: hs-i2c6-bus-pins {
|
||||
samsung,pins = "gpb1-4", "gpb1-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c7_bus: hs-i2c7-bus-pins {
|
||||
samsung,pins = "gpb1-6", "gpb1-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart0_data: uart0-data-pins {
|
||||
samsung,pins = "gpb7-0", "gpb7-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_data: uart1-data-pins {
|
||||
samsung,pins = "gpb7-4", "gpb7-5";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi0_bus: spi0-bus-pins {
|
||||
samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi1_bus: spi1-bus-pins {
|
||||
samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi2_bus: spi2-bus-pins {
|
||||
samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_pmu {
|
||||
gpq0: gpq0-gpio-bank {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,731 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Tesla Full Self-Driving SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
|
||||
* https://www.samsung.com
|
||||
* Copyright (c) 2017-2022 Tesla, Inc.
|
||||
* https://www.tesla.com
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/fsd-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "tesla,fsd";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &hsi2c_0;
|
||||
i2c1 = &hsi2c_1;
|
||||
i2c2 = &hsi2c_2;
|
||||
i2c3 = &hsi2c_3;
|
||||
i2c4 = &hsi2c_4;
|
||||
i2c5 = &hsi2c_5;
|
||||
i2c6 = &hsi2c_6;
|
||||
i2c7 = &hsi2c_7;
|
||||
pinctrl0 = &pinctrl_fsys0;
|
||||
pinctrl1 = &pinctrl_peric;
|
||||
pinctrl2 = &pinctrl_pmu;
|
||||
spi0 = &spi_0;
|
||||
spi1 = &spi_1;
|
||||
spi2 = &spi_2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpucl0_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpucl0_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpucl0_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpucl0_3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpucl1_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpucl1_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpucl1_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpucl1_3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&cpucl2_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpucl2_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpucl2_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpucl2_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Cluster 0 */
|
||||
cpucl0_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x000>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl0_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x001>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl0_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x002>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl0_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x003>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
/* Cluster 1 */
|
||||
cpucl1_0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl1_1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl1_2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl1_3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
/* Cluster 2 */
|
||||
cpucl2_0: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl2_1: cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x201>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl2_2: cpu@202 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x202>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
cpucl2_3: cpu@203 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x203>;
|
||||
enable-method = "psci";
|
||||
clock-frequency = <2400000000>;
|
||||
cpu-idle-states = <&CPU_SLEEP>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_SLEEP: cpu-sleep {
|
||||
idle-state-name = "c2";
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <30>;
|
||||
exit-latency-us = <75>;
|
||||
min-residency-us = <300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
|
||||
<&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
|
||||
<&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
|
||||
<&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
fin_pll: clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "fin_pll";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
|
||||
|
||||
gic: interrupt-controller@10400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
|
||||
<0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
smmu_imem: iommu@10200000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0x10200000 0x0 0x10000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <7>;
|
||||
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
|
||||
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
|
||||
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
|
||||
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
|
||||
/* Performance counter interrupts */
|
||||
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
|
||||
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
|
||||
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
|
||||
/* Per context non-secure context interrupts, 0-3 interrupts */
|
||||
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
|
||||
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
|
||||
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
|
||||
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
|
||||
};
|
||||
|
||||
smmu_isp: iommu@12100000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0x12100000 0x0 0x10000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <11>;
|
||||
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
|
||||
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
|
||||
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
|
||||
/* Performance counter interrupts */
|
||||
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
|
||||
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
|
||||
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
|
||||
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
|
||||
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
|
||||
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
|
||||
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
|
||||
/* Per context non-secure context interrupts, 0-7 interrupts */
|
||||
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
|
||||
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
|
||||
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
|
||||
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
|
||||
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
|
||||
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
|
||||
};
|
||||
|
||||
smmu_peric: iommu@14900000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0x14900000 0x0 0x10000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <5>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
|
||||
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
|
||||
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
|
||||
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
|
||||
/* Performance counter interrupts */
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
|
||||
/* Per context non-secure context interrupts, 0-1 interrupts */
|
||||
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
|
||||
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
|
||||
};
|
||||
|
||||
smmu_fsys0: iommu@15450000 {
|
||||
compatible = "arm,mmu-500";
|
||||
reg = <0x0 0x15450000 0x0 0x10000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <5>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
|
||||
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
|
||||
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
|
||||
/* Performance counter interrupts */
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
|
||||
/* Per context non-secure context interrupts, 0-1 interrupts */
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
|
||||
};
|
||||
|
||||
clock_imem: clock-controller@10010000 {
|
||||
compatible = "tesla,fsd-clock-imem";
|
||||
reg = <0x0 0x10010000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
|
||||
<&clock_cmu DOUT_CMU_IMEM_ACLK>,
|
||||
<&clock_cmu DOUT_CMU_IMEM_DMACLK>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_imem_tcuclk",
|
||||
"dout_cmu_imem_aclk",
|
||||
"dout_cmu_imem_dmaclk";
|
||||
};
|
||||
|
||||
clock_cmu: clock-controller@11c10000 {
|
||||
compatible = "tesla,fsd-clock-cmu";
|
||||
reg = <0x0 0x11c10000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "fin_pll";
|
||||
};
|
||||
|
||||
clock_csi: clock-controller@12610000 {
|
||||
compatible = "tesla,fsd-clock-cam_csi";
|
||||
reg = <0x0 0x12610000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "fin_pll";
|
||||
};
|
||||
|
||||
clock_mfc: clock-controller@12810000 {
|
||||
compatible = "tesla,fsd-clock-mfc";
|
||||
reg = <0x0 0x12810000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "fin_pll";
|
||||
};
|
||||
|
||||
clock_peric: clock-controller@14010000 {
|
||||
compatible = "tesla,fsd-clock-peric";
|
||||
reg = <0x0 0x14010000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
|
||||
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
|
||||
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
|
||||
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
|
||||
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_pll_shared0_div4",
|
||||
"dout_cmu_peric_shared1div36",
|
||||
"dout_cmu_peric_shared0div3_tbuclk",
|
||||
"dout_cmu_peric_shared0div20",
|
||||
"dout_cmu_peric_shared1div4_dmaclk";
|
||||
};
|
||||
|
||||
clock_fsys0: clock-controller@15010000 {
|
||||
compatible = "tesla,fsd-clock-fsys0";
|
||||
reg = <0x0 0x15010000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
|
||||
<&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
|
||||
<&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_pll_shared0_div6",
|
||||
"dout_cmu_fsys0_shared1div4",
|
||||
"dout_cmu_fsys0_shared0div4";
|
||||
};
|
||||
|
||||
clock_fsys1: clock-controller@16810000 {
|
||||
compatible = "tesla,fsd-clock-fsys1";
|
||||
reg = <0x0 0x16810000 0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_fsys1_shared0div8",
|
||||
"dout_cmu_fsys1_shared0div4";
|
||||
};
|
||||
|
||||
mdma0: dma-controller@10100000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x10100000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
|
||||
clock-names = "apb_pclk";
|
||||
iommus = <&smmu_imem 0x800 0x0>;
|
||||
};
|
||||
|
||||
mdma1: dma-controller@10110000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x10110000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
|
||||
clock-names = "apb_pclk";
|
||||
iommus = <&smmu_imem 0x801 0x0>;
|
||||
};
|
||||
|
||||
pdma0: dma-controller@14280000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x14280000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
|
||||
clock-names = "apb_pclk";
|
||||
iommus = <&smmu_peric 0x2 0x0>;
|
||||
};
|
||||
|
||||
pdma1: dma-controller@14290000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x14290000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
|
||||
clock-names = "apb_pclk";
|
||||
iommus = <&smmu_peric 0x1 0x0>;
|
||||
};
|
||||
|
||||
serial_0: serial@14180000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x0 0x14180000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma1 1>, <&pdma1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clock_peric PERIC_PCLK_UART0>,
|
||||
<&clock_peric PERIC_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial_1: serial@14190000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x0 0x14190000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma1 3>, <&pdma1 2>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clock_peric PERIC_PCLK_UART1>,
|
||||
<&clock_peric PERIC_SCLK_UART1>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@11400000 {
|
||||
compatible = "samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x0 0x11400000 0x0 0x5000>;
|
||||
};
|
||||
|
||||
watchdog_0: watchdog@100a0000 {
|
||||
compatible = "samsung,exynos7-wdt";
|
||||
reg = <0x0 0x100a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
watchdog_1: watchdog@100b0000 {
|
||||
compatible = "samsung,exynos7-wdt";
|
||||
reg = <0x0 0x100b0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
watchdog_2: watchdog@100c0000 {
|
||||
compatible = "samsung,exynos7-wdt";
|
||||
reg = <0x0 0x100c0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
clocks = <&fin_pll>;
|
||||
clock-names = "watchdog";
|
||||
};
|
||||
|
||||
pwm_0: pwm@14100000 {
|
||||
compatible = "samsung,exynos4210-pwm";
|
||||
reg = <0x0 0x14100000 0x0 0x100>;
|
||||
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
|
||||
clock-names = "timers";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm_1: pwm@14110000 {
|
||||
compatible = "samsung,exynos4210-pwm";
|
||||
reg = <0x0 0x14110000 0x0 0x100>;
|
||||
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
|
||||
clock-names = "timers";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_0: i2c@14200000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14200000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c0_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_1: i2c@14210000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14210000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c1_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_2: i2c@14220000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14220000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c2_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_3: i2c@14230000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14230000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c3_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_4: i2c@14240000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14240000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c4_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_5: i2c@14250000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14250000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c5_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_6: i2c@14260000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14260000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c6_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_7: i2c@14270000 {
|
||||
compatible = "samsung,exynos7-hsi2c";
|
||||
reg = <0x0 0x14270000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hs_i2c7_bus>;
|
||||
clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
|
||||
clock-names = "hsi2c";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_pmu: pinctrl@114f0000 {
|
||||
compatible = "tesla,fsd-pinctrl";
|
||||
reg = <0x0 0x114f0000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_peric: pinctrl@141f0000 {
|
||||
compatible = "tesla,fsd-pinctrl";
|
||||
reg = <0x0 0x141f0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys0: pinctrl@15020000 {
|
||||
compatible = "tesla,fsd-pinctrl";
|
||||
reg = <0x0 0x15020000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi_0: spi@14140000 {
|
||||
compatible = "tesla,fsd-spi";
|
||||
reg = <0x0 0x14140000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma1 4>, <&pdma1 5>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock_peric PERIC_PCLK_SPI0>,
|
||||
<&clock_peric PERIC_SCLK_SPI0>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
samsung,spi-src-clk = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_bus>;
|
||||
num-cs = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_1: spi@14150000 {
|
||||
compatible = "tesla,fsd-spi";
|
||||
reg = <0x0 0x14150000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma1 6>, <&pdma1 7>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock_peric PERIC_PCLK_SPI1>,
|
||||
<&clock_peric PERIC_SCLK_SPI1>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
samsung,spi-src-clk = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_bus>;
|
||||
num-cs = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi_2: spi@14160000 {
|
||||
compatible = "tesla,fsd-spi";
|
||||
reg = <0x0 0x14160000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&pdma1 8>, <&pdma1 9>;
|
||||
dma-names = "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clock_peric PERIC_PCLK_SPI2>,
|
||||
<&clock_peric PERIC_SCLK_SPI2>;
|
||||
clock-names = "spi", "spi_busclk0";
|
||||
samsung,spi-src-clk = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_bus>;
|
||||
num-cs = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "fsd-pinctrl.dtsi"
|
||||
|
|
@ -54,6 +54,7 @@ CONFIG_ARCH_SEATTLE=y
|
|||
CONFIG_ARCH_INTEL_SOCFPGA=y
|
||||
CONFIG_ARCH_SYNQUACER=y
|
||||
CONFIG_ARCH_TEGRA=y
|
||||
CONFIG_ARCH_TESLA_FSD=y
|
||||
CONFIG_ARCH_SPRD=y
|
||||
CONFIG_ARCH_THUNDER=y
|
||||
CONFIG_ARCH_THUNDER2=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,150 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
|
||||
* https://www.samsung.com
|
||||
* Copyright (c) 2017-2022 Tesla, Inc.
|
||||
* https://www.tesla.com
|
||||
*
|
||||
* The constants defined in this header are being used in dts
|
||||
* and fsd platform driver.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_FSD_H
|
||||
#define _DT_BINDINGS_CLOCK_FSD_H
|
||||
|
||||
/* CMU */
|
||||
#define DOUT_CMU_PLL_SHARED0_DIV4 1
|
||||
#define DOUT_CMU_PERIC_SHARED1DIV36 2
|
||||
#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
|
||||
#define DOUT_CMU_PERIC_SHARED0DIV20 4
|
||||
#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
|
||||
#define DOUT_CMU_PLL_SHARED0_DIV6 6
|
||||
#define DOUT_CMU_FSYS0_SHARED1DIV4 7
|
||||
#define DOUT_CMU_FSYS0_SHARED0DIV4 8
|
||||
#define DOUT_CMU_FSYS1_SHARED0DIV8 9
|
||||
#define DOUT_CMU_FSYS1_SHARED0DIV4 10
|
||||
#define CMU_CPUCL_SWITCH_GATE 11
|
||||
#define DOUT_CMU_IMEM_TCUCLK 12
|
||||
#define DOUT_CMU_IMEM_ACLK 13
|
||||
#define DOUT_CMU_IMEM_DMACLK 14
|
||||
#define GAT_CMU_FSYS0_SHARED0DIV4 15
|
||||
#define CMU_NR_CLK 16
|
||||
|
||||
/* PERIC */
|
||||
#define PERIC_SCLK_UART0 1
|
||||
#define PERIC_PCLK_UART0 2
|
||||
#define PERIC_SCLK_UART1 3
|
||||
#define PERIC_PCLK_UART1 4
|
||||
#define PERIC_DMA0_IPCLKPORT_ACLK 5
|
||||
#define PERIC_DMA1_IPCLKPORT_ACLK 6
|
||||
#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
|
||||
#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
|
||||
#define PERIC_PCLK_SPI0 9
|
||||
#define PERIC_SCLK_SPI0 10
|
||||
#define PERIC_PCLK_SPI1 11
|
||||
#define PERIC_SCLK_SPI1 12
|
||||
#define PERIC_PCLK_SPI2 13
|
||||
#define PERIC_SCLK_SPI2 14
|
||||
#define PERIC_PCLK_TDM0 15
|
||||
#define PERIC_PCLK_HSI2C0 16
|
||||
#define PERIC_PCLK_HSI2C1 17
|
||||
#define PERIC_PCLK_HSI2C2 18
|
||||
#define PERIC_PCLK_HSI2C3 19
|
||||
#define PERIC_PCLK_HSI2C4 20
|
||||
#define PERIC_PCLK_HSI2C5 21
|
||||
#define PERIC_PCLK_HSI2C6 22
|
||||
#define PERIC_PCLK_HSI2C7 23
|
||||
#define PERIC_MCAN0_IPCLKPORT_CCLK 24
|
||||
#define PERIC_MCAN0_IPCLKPORT_PCLK 25
|
||||
#define PERIC_MCAN1_IPCLKPORT_CCLK 26
|
||||
#define PERIC_MCAN1_IPCLKPORT_PCLK 27
|
||||
#define PERIC_MCAN2_IPCLKPORT_CCLK 28
|
||||
#define PERIC_MCAN2_IPCLKPORT_PCLK 29
|
||||
#define PERIC_MCAN3_IPCLKPORT_CCLK 30
|
||||
#define PERIC_MCAN3_IPCLKPORT_PCLK 31
|
||||
#define PERIC_PCLK_ADCIF 32
|
||||
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
|
||||
#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
|
||||
#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
|
||||
#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
|
||||
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
|
||||
#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
|
||||
#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
|
||||
#define PERIC_HCLK_TDM0 40
|
||||
#define PERIC_PCLK_TDM1 41
|
||||
#define PERIC_HCLK_TDM1 42
|
||||
#define PERIC_EQOS_PHYRXCLK_MUX 43
|
||||
#define PERIC_EQOS_PHYRXCLK 44
|
||||
#define PERIC_DOUT_RGMII_CLK 45
|
||||
#define PERIC_NR_CLK 46
|
||||
|
||||
/* FSYS0 */
|
||||
#define UFS0_MPHY_REFCLK_IXTAL24 1
|
||||
#define UFS0_MPHY_REFCLK_IXTAL26 2
|
||||
#define UFS1_MPHY_REFCLK_IXTAL24 3
|
||||
#define UFS1_MPHY_REFCLK_IXTAL26 4
|
||||
#define UFS0_TOP0_HCLK_BUS 5
|
||||
#define UFS0_TOP0_ACLK 6
|
||||
#define UFS0_TOP0_CLK_UNIPRO 7
|
||||
#define UFS0_TOP0_FMP_CLK 8
|
||||
#define UFS1_TOP1_HCLK_BUS 9
|
||||
#define UFS1_TOP1_ACLK 10
|
||||
#define UFS1_TOP1_CLK_UNIPRO 11
|
||||
#define UFS1_TOP1_FMP_CLK 12
|
||||
#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
|
||||
#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
|
||||
#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
|
||||
#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
|
||||
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
|
||||
#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
|
||||
#define FSYS0_NR_CLK 23
|
||||
|
||||
/* FSYS1 */
|
||||
#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
|
||||
#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
|
||||
#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
|
||||
#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
|
||||
#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
|
||||
#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
|
||||
#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
|
||||
#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
|
||||
#define FSYS1_NR_CLK 9
|
||||
|
||||
/* IMEM */
|
||||
#define IMEM_DMA0_IPCLKPORT_ACLK 1
|
||||
#define IMEM_DMA1_IPCLKPORT_ACLK 2
|
||||
#define IMEM_WDT0_IPCLKPORT_PCLK 3
|
||||
#define IMEM_WDT1_IPCLKPORT_PCLK 4
|
||||
#define IMEM_WDT2_IPCLKPORT_PCLK 5
|
||||
#define IMEM_MCT_PCLK 6
|
||||
#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
|
||||
#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
|
||||
#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
|
||||
#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
|
||||
#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
|
||||
#define IMEM_NR_CLK 12
|
||||
|
||||
/* MFC */
|
||||
#define MFC_MFC_IPCLKPORT_ACLK 1
|
||||
#define MFC_NR_CLK 2
|
||||
|
||||
/* CAM_CSI */
|
||||
#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
|
||||
#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
|
||||
#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
|
||||
#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
|
||||
#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
|
||||
#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
|
||||
#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
|
||||
#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
|
||||
#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
|
||||
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
|
||||
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
|
||||
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
|
||||
#define CAM_CSI_NR_CLK 13
|
||||
|
||||
#endif /*_DT_BINDINGS_CLOCK_FSD_H */
|
||||
Loading…
Reference in New Issue