dt-bindings: Consolidate ChipIdea USB ci13xxx bindings
Combine the ChipIdea USB binding into a single document to reduce duplication and fragmentation. This marks use of the old PHY bindings as deprecated. Future compatible bindings should use generic PHY binding. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Ivan T. Ivanov <iivanov@mm-sol.com> Cc: Peter Chen <peter.chen@freescale.com> Cc: Daniel Tang <dt.tangr@gmail.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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* Freescale i.MX ci13xxx usb controllers
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Required properties:
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- compatible: Should be "fsl,imx27-usb"
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- reg: Should contain registers location and length
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- interrupts: Should contain controller interrupt
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- fsl,usbphy: phandle of usb phy that connects to the port
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Recommended properies:
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- phy_type: the type of the phy connected to the core. Should be one
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of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
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property the PORTSC register won't be touched
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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Optional properties:
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- fsl,usbmisc: phandler of non-core register device, with one argument
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that indicate usb controller index
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- vbus-supply: regulator for vbus
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- disable-over-current: disable over current detect
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- external-vbus-divider: enables off-chip resistor divider for Vbus
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- maximum-speed: limit the maximum connection speed to "full-speed".
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- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
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Examples:
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usb@02184000 { /* USB OTG */
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compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
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reg = <0x02184000 0x200>;
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interrupts = <0 43 0x04>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc 0>;
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disable-over-current;
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external-vbus-divider;
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maximum-speed = "full-speed";
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tpl-support;
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};
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Qualcomm CI13xxx (Chipidea) USB controllers
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Required properties:
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- compatible: should contain "qcom,ci-hdrc"
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- reg: offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the controller interrupt.
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- usb-phy: phandle for the PHY device
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- dr_mode: Should be "peripheral"
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Examples:
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gadget@f9a55000 {
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compatible = "qcom,ci-hdrc";
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reg = <0xf9a55000 0x400>;
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dr_mode = "peripheral";
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interrupts = <0 134 0>;
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usb-phy = <&usbphy0>;
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};
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* USB2 ChipIdea USB controller for ci13xxx
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Required properties:
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- compatible: should be "chipidea,usb2"
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- compatible: should be one of:
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"fsl,imx27-usb"
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"lsi,zevio-usb"
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"qcom,ci-hdrc"
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"chipidea,usb2"
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- reg: base address and length of the registers
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- interrupts: interrupt for the USB controller
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Recommended properies:
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- phy_type: the type of the phy connected to the core. Should be one
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of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
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property the PORTSC register won't be touched.
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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Deprecated properties:
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- usb-phy: phandle for the PHY device. Use "phys" instead.
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- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
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Optional properties:
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- clocks: reference to the USB clock
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- phys: reference to the USB PHY
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- phy-names: should be "usb-phy"
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- vbus-supply: reference to the VBUS regulator
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- maximum-speed: limit the maximum connection speed to "full-speed".
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- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
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- fsl,usbmisc: (FSL only) phandler of non-core register device, with one
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argument that indicate usb controller index
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- disable-over-current: (FSL only) disable over current detect
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- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
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Example:
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* LSI Zevio USB OTG Controller
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Required properties:
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- compatible: Should be "lsi,zevio-usb"
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- reg: Should contain registers location and length
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- interrupts: Should contain controller interrupt
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Optional properties:
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- vbus-supply: regulator for vbus
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Examples:
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usb0: usb@b0000000 {
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reg = <0xb0000000 0x1000>;
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compatible = "lsi,zevio-usb";
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interrupts = <8>;
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vbus-supply = <&vbus_reg>;
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};
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