fbdev: bfin-lq035q1-fb: new Blackfin Landscape LCD EZ-Extender driver
Framebuffer driver for the Landscape LCD EZ-Extender (ADZS-BFLLCD-EZEXT) http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:landscape_lcd_ez-extender Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Michael Hennerich
Linus Torvalds
parent
0769746183
commit
9cfe4a93e5
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@ -0,0 +1,28 @@
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/*
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* Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
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*
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* Copyright 2008-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef BFIN_LQ035Q1_H
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#define BFIN_LQ035Q1_H
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#define LQ035_RL (0 << 8) /* Right -> Left Scan */
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#define LQ035_LR (1 << 8) /* Left -> Right Scan */
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#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
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#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
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#define LQ035_BGR (1 << 11) /* Use BGR format */
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#define LQ035_RGB (0 << 11) /* Use RGB format */
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#define LQ035_NORM (1 << 13) /* Reversal */
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#define LQ035_REV (0 << 13) /* Reversal */
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struct bfin_lq035q1fb_disp_info {
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unsigned mode;
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/* GPIOs */
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int use_bl;
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unsigned gpio_bl;
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};
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#endif /* BFIN_LQ035Q1_H */
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@ -614,6 +614,21 @@ config FB_BFIN_T350MCQB
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This display is a QVGA 320x240 24-bit RGB display interfaced by an 8-bit wide PPI
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It uses PPI[0..7] PPI_FS1, PPI_FS2 and PPI_CLK.
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config FB_BFIN_LQ035Q1
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tristate "SHARP LQ035Q1DH02 TFT LCD"
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depends on FB && BLACKFIN && SPI
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select FB_CFB_FILLRECT
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select FB_CFB_COPYAREA
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select FB_CFB_IMAGEBLIT
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select BFIN_GPTIMERS
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help
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This is the framebuffer device driver for a SHARP LQ035Q1DH02 TFT display found on
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the Blackfin Landscape LCD EZ-Extender Card.
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This display is a QVGA 320x240 18-bit RGB display interfaced by an 16-bit wide PPI
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It uses PPI[0..15] PPI_FS1, PPI_FS2 and PPI_CLK.
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To compile this driver as a module, choose M here: the
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module will be called bfin-lq035q1-fb.
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config FB_STI
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tristate "HP STI frame buffer device support"
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@ -137,6 +137,7 @@ obj-$(CONFIG_FB_EFI) += efifb.o
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obj-$(CONFIG_FB_VGA16) += vga16fb.o
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obj-$(CONFIG_FB_OF) += offb.o
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obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
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obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
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obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
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obj-$(CONFIG_FB_MX3) += mx3fb.o
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obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
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@ -0,0 +1,826 @@
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/*
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* Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
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*
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* Copyright 2008-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#define DRIVER_NAME "bfin-lq035q1"
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#define pr_fmt(fmt) DRIVER_NAME ": " fmt
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/backlight.h>
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#include <linux/lcd.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/dma-mapping.h>
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#include <asm/blackfin.h>
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#include <asm/irq.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#include <asm/gptimers.h>
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#include <asm/bfin-lq035q1.h>
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#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
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#define TIMER_HSYNC_id TIMER1_id
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#define TIMER_HSYNCbit TIMER1bit
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#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
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#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
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#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
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#define TIMER_VSYNC_id TIMER2_id
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#define TIMER_VSYNCbit TIMER2bit
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#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2
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#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2
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#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2
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#else
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#define TIMER_HSYNC_id TIMER0_id
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#define TIMER_HSYNCbit TIMER0bit
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#define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0
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#define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0
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#define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0
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#define TIMER_VSYNC_id TIMER1_id
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#define TIMER_VSYNCbit TIMER1bit
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#define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1
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#define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1
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#define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1
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#endif
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#define LCD_X_RES 320 /* Horizontal Resolution */
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#define LCD_Y_RES 240 /* Vertical Resolution */
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#define DMA_BUS_SIZE 16
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#define USE_RGB565_16_BIT_PPI
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#ifdef USE_RGB565_16_BIT_PPI
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#define LCD_BPP 16 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 1
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#define CPLD_PIPELINE_DELAY_COR 0 /* NO CPLB */
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#endif
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/* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD)
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* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
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*/
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#ifdef USE_RGB565_8_BIT_PPI
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#define LCD_BPP 16 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 2
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#define CPLD_PIPELINE_DELAY_COR 3 /* RGB565 */
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#endif
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#ifdef USE_RGB888_8_BIT_PPI
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#define LCD_BPP 24 /* Bit Per Pixel */
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#define CLOCKS_PER_PIX 3
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#define CPLD_PIPELINE_DELAY_COR 5 /* RGB888 */
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#endif
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/*
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* HS and VS timing parameters (all in number of PPI clk ticks)
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*/
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#define U_LINE 4 /* Blanking Lines */
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#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
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#define H_PERIOD (336 * CLOCKS_PER_PIX) /* HS period */
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#define H_PULSE (2 * CLOCKS_PER_PIX) /* HS pulse width */
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#define H_START (7 * CLOCKS_PER_PIX + CPLD_PIPELINE_DELAY_COR) /* first valid pixel */
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#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
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#define V_PULSE (2 * CLOCKS_PER_PIX) /* VS pulse width (1-5 H_PERIODs) */
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#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
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#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
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#define BFIN_LCD_NBR_PALETTE_ENTRIES 256
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#define PPI_TX_MODE 0x2
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#define PPI_XFER_TYPE_11 0xC
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#define PPI_PORT_CFG_01 0x10
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#define PPI_POLS_1 0x8000
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#if (CLOCKS_PER_PIX > 1)
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#define PPI_PMODE (DLEN_8 | PACK_EN)
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#else
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#define PPI_PMODE (DLEN_16)
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#endif
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#define LQ035_INDEX 0x74
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#define LQ035_DATA 0x76
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#define LQ035_DRIVER_OUTPUT_CTL 0x1
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#define LQ035_SHUT_CTL 0x11
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#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
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#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
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#define LQ035_SHUT (1 << 0) /* Shutdown */
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#define LQ035_ON (0 << 0) /* Shutdown */
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struct bfin_lq035q1fb_info {
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struct fb_info *fb;
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struct device *dev;
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struct spi_driver spidrv;
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struct bfin_lq035q1fb_disp_info *disp_info;
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unsigned char *fb_buffer; /* RGB Buffer */
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dma_addr_t dma_handle;
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int lq035_open_cnt;
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int irq;
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spinlock_t lock; /* lock */
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u32 pseudo_pal[16];
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};
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static int nocursor;
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module_param(nocursor, int, 0644);
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MODULE_PARM_DESC(nocursor, "cursor enable/disable");
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struct spi_control {
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unsigned short mode;
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};
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static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value)
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{
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int ret;
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u8 regs[3] = { LQ035_INDEX, 0, 0 };
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u8 dat[3] = { LQ035_DATA, 0, 0 };
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if (!spi)
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return -ENODEV;
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regs[2] = reg;
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dat[1] = value >> 8;
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dat[2] = value & 0xFF;
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ret = spi_write(spi, regs, ARRAY_SIZE(regs));
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ret |= spi_write(spi, dat, ARRAY_SIZE(dat));
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return ret;
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}
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static int __devinit lq035q1_spidev_probe(struct spi_device *spi)
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{
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int ret;
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struct spi_control *ctl;
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struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver,
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struct bfin_lq035q1fb_info,
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spidrv.driver);
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ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
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if (!ctl)
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return -ENOMEM;
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ctl->mode = (info->disp_info->mode &
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LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT;
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ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
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ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
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if (ret)
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return ret;
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spi_set_drvdata(spi, ctl);
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return 0;
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}
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static int lq035q1_spidev_remove(struct spi_device *spi)
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{
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return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
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}
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#ifdef CONFIG_PM
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static int lq035q1_spidev_suspend(struct spi_device *spi, pm_message_t state)
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{
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return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
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}
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static int lq035q1_spidev_resume(struct spi_device *spi)
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{
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int ret;
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struct spi_control *ctl = spi_get_drvdata(spi);
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ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode);
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if (ret)
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return ret;
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return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON);
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}
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#else
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# define lq035q1_spidev_suspend NULL
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# define lq035q1_spidev_resume NULL
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#endif
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/* Power down all displays on reboot, poweroff or halt */
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static void lq035q1_spidev_shutdown(struct spi_device *spi)
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{
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lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT);
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}
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static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg)
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{
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if (info->disp_info->use_bl)
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gpio_set_value(info->disp_info->gpio_bl, arg);
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return 0;
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}
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static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi)
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{
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bfin_write_PPI_DELAY(H_START);
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bfin_write_PPI_COUNT(H_ACTPIX - 1);
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bfin_write_PPI_FRAME(V_LINES);
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bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */
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PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
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PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
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PPI_PMODE | /* 8/16 bit data length / PACK_EN? */
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PPI_POLS_1); /* faling edge syncs POLS */
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}
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static inline void bfin_lq035q1_disable_ppi(void)
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{
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bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
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}
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static inline void bfin_lq035q1_enable_ppi(void)
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{
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bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
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}
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static void bfin_lq035q1_start_timers(void)
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{
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enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit);
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}
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static void bfin_lq035q1_stop_timers(void)
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{
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disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit);
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set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN |
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TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL |
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TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF);
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}
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static void bfin_lq035q1_init_timers(void)
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{
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bfin_lq035q1_stop_timers();
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set_gptimer_period(TIMER_HSYNC_id, H_PERIOD);
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set_gptimer_pwidth(TIMER_HSYNC_id, H_PULSE);
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set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
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TIMER_TIN_SEL | TIMER_CLK_SEL|
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TIMER_EMU_RUN);
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set_gptimer_period(TIMER_VSYNC_id, V_PERIOD);
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set_gptimer_pwidth(TIMER_VSYNC_id, V_PULSE);
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set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT |
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TIMER_TIN_SEL | TIMER_CLK_SEL |
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TIMER_EMU_RUN);
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}
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static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi)
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{
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set_dma_config(CH_PPI,
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set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
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INTR_DISABLE, DIMENSION_2D,
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DATA_SIZE_16,
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DMA_NOSYNC_KEEP_DMA_BUF));
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set_dma_x_count(CH_PPI, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
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set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8);
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set_dma_y_count(CH_PPI, V_LINES);
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set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8);
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set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer);
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}
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#if (CLOCKS_PER_PIX == 1)
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static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
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P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
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P_PPI0_D6, P_PPI0_D7, P_PPI0_D8,
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P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
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P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
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P_PPI0_D15, 0};
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#else
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static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
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P_PPI0_D0, P_PPI0_D1, P_PPI0_D2,
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P_PPI0_D3, P_PPI0_D4, P_PPI0_D5,
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P_PPI0_D6, P_PPI0_D7, 0};
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#endif
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static inline void bfin_lq035q1_free_ports(void)
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{
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peripheral_free_list(ppi0_req_16);
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if (ANOMALY_05000400)
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gpio_free(P_IDENT(P_PPI0_FS3));
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}
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static int __devinit bfin_lq035q1_request_ports(struct platform_device *pdev)
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{
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/* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode:
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* Drive PPI_FS3 Low
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*/
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if (ANOMALY_05000400) {
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int ret = gpio_request(P_IDENT(P_PPI0_FS3), "PPI_FS3");
|
||||
if (ret)
|
||||
return ret;
|
||||
gpio_direction_output(P_IDENT(P_PPI0_FS3), 0);
|
||||
}
|
||||
|
||||
if (peripheral_request_list(ppi0_req_16, DRIVER_NAME)) {
|
||||
dev_err(&pdev->dev, "requesting peripherals failed\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_open(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
fbi->lq035_open_cnt++;
|
||||
|
||||
if (fbi->lq035_open_cnt <= 1) {
|
||||
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
|
||||
bfin_lq035q1_config_dma(fbi);
|
||||
bfin_lq035q1_config_ppi(fbi);
|
||||
bfin_lq035q1_init_timers();
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_lq035q1_start_timers();
|
||||
lq035q1_backlight(fbi, 1);
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_release(struct fb_info *info, int user)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *fbi = info->par;
|
||||
|
||||
spin_lock(&fbi->lock);
|
||||
|
||||
fbi->lq035_open_cnt--;
|
||||
|
||||
if (fbi->lq035_open_cnt <= 0) {
|
||||
lq035q1_backlight(fbi, 0);
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_lq035q1_stop_timers();
|
||||
}
|
||||
|
||||
spin_unlock(&fbi->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info)
|
||||
{
|
||||
switch (var->bits_per_pixel) {
|
||||
#if (LCD_BPP == 24)
|
||||
case 24:/* TRUECOLOUR, 16m */
|
||||
#else
|
||||
case 16:/* DIRECTCOLOUR, 64k */
|
||||
#endif
|
||||
var->red.offset = info->var.red.offset;
|
||||
var->green.offset = info->var.green.offset;
|
||||
var->blue.offset = info->var.blue.offset;
|
||||
var->red.length = info->var.red.length;
|
||||
var->green.length = info->var.green.length;
|
||||
var->blue.length = info->var.blue.length;
|
||||
var->transp.offset = 0;
|
||||
var->transp.length = 0;
|
||||
var->transp.msb_right = 0;
|
||||
var->red.msb_right = 0;
|
||||
var->green.msb_right = 0;
|
||||
var->blue.msb_right = 0;
|
||||
break;
|
||||
default:
|
||||
pr_debug("%s: depth not supported: %u BPP\n", __func__,
|
||||
var->bits_per_pixel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (info->var.xres != var->xres || info->var.yres != var->yres ||
|
||||
info->var.xres_virtual != var->xres_virtual ||
|
||||
info->var.yres_virtual != var->yres_virtual) {
|
||||
pr_debug("%s: Resolution not supported: X%u x Y%u \n",
|
||||
__func__, var->xres, var->yres);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
||||
if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
|
||||
pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
|
||||
__func__, var->yres_virtual);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
|
||||
{
|
||||
if (nocursor)
|
||||
return 0;
|
||||
else
|
||||
return -EINVAL; /* just to force soft_cursor() call */
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green,
|
||||
u_int blue, u_int transp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
if (info->var.grayscale) {
|
||||
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
|
||||
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
|
||||
}
|
||||
|
||||
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
|
||||
|
||||
u32 value;
|
||||
/* Place color in the pseudopalette */
|
||||
if (regno > 16)
|
||||
return -EINVAL;
|
||||
|
||||
red >>= (16 - info->var.red.length);
|
||||
green >>= (16 - info->var.green.length);
|
||||
blue >>= (16 - info->var.blue.length);
|
||||
|
||||
value = (red << info->var.red.offset) |
|
||||
(green << info->var.green.offset) |
|
||||
(blue << info->var.blue.offset);
|
||||
value &= 0xFFFFFF;
|
||||
|
||||
((u32 *) (info->pseudo_palette))[regno] = value;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops bfin_lq035q1_fb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_open = bfin_lq035q1_fb_open,
|
||||
.fb_release = bfin_lq035q1_fb_release,
|
||||
.fb_check_var = bfin_lq035q1_fb_check_var,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
.fb_cursor = bfin_lq035q1_fb_cursor,
|
||||
.fb_setcolreg = bfin_lq035q1_fb_setcolreg,
|
||||
};
|
||||
|
||||
static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id)
|
||||
{
|
||||
/*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/
|
||||
|
||||
u16 status = bfin_read_PPI_STATUS();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
|
||||
if (status) {
|
||||
bfin_lq035q1_disable_ppi();
|
||||
disable_dma(CH_PPI);
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __devinit bfin_lq035q1_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bfin_lq035q1fb_info *info;
|
||||
struct fb_info *fbinfo;
|
||||
int ret;
|
||||
|
||||
ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI");
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "PPI DMA unavailable\n");
|
||||
goto out1;
|
||||
}
|
||||
|
||||
fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev);
|
||||
if (!fbinfo) {
|
||||
ret = -ENOMEM;
|
||||
goto out2;
|
||||
}
|
||||
|
||||
info = fbinfo->par;
|
||||
info->fb = fbinfo;
|
||||
info->dev = &pdev->dev;
|
||||
|
||||
info->disp_info = pdev->dev.platform_data;
|
||||
|
||||
platform_set_drvdata(pdev, fbinfo);
|
||||
|
||||
strcpy(fbinfo->fix.id, DRIVER_NAME);
|
||||
|
||||
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
|
||||
fbinfo->fix.type_aux = 0;
|
||||
fbinfo->fix.xpanstep = 0;
|
||||
fbinfo->fix.ypanstep = 0;
|
||||
fbinfo->fix.ywrapstep = 0;
|
||||
fbinfo->fix.accel = FB_ACCEL_NONE;
|
||||
fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
|
||||
|
||||
fbinfo->var.nonstd = 0;
|
||||
fbinfo->var.activate = FB_ACTIVATE_NOW;
|
||||
fbinfo->var.height = -1;
|
||||
fbinfo->var.width = -1;
|
||||
fbinfo->var.accel_flags = 0;
|
||||
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
|
||||
|
||||
fbinfo->var.xres = LCD_X_RES;
|
||||
fbinfo->var.xres_virtual = LCD_X_RES;
|
||||
fbinfo->var.yres = LCD_Y_RES;
|
||||
fbinfo->var.yres_virtual = LCD_Y_RES;
|
||||
fbinfo->var.bits_per_pixel = LCD_BPP;
|
||||
|
||||
if (info->disp_info->mode & LQ035_BGR) {
|
||||
#if (LCD_BPP == 24)
|
||||
fbinfo->var.red.offset = 0;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 16;
|
||||
#else
|
||||
fbinfo->var.red.offset = 0;
|
||||
fbinfo->var.green.offset = 5;
|
||||
fbinfo->var.blue.offset = 11;
|
||||
#endif
|
||||
} else {
|
||||
#if (LCD_BPP == 24)
|
||||
fbinfo->var.red.offset = 16;
|
||||
fbinfo->var.green.offset = 8;
|
||||
fbinfo->var.blue.offset = 0;
|
||||
#else
|
||||
fbinfo->var.red.offset = 11;
|
||||
fbinfo->var.green.offset = 5;
|
||||
fbinfo->var.blue.offset = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
fbinfo->var.transp.offset = 0;
|
||||
|
||||
#if (LCD_BPP == 24)
|
||||
fbinfo->var.red.length = 8;
|
||||
fbinfo->var.green.length = 8;
|
||||
fbinfo->var.blue.length = 8;
|
||||
#else
|
||||
fbinfo->var.red.length = 5;
|
||||
fbinfo->var.green.length = 6;
|
||||
fbinfo->var.blue.length = 5;
|
||||
#endif
|
||||
|
||||
fbinfo->var.transp.length = 0;
|
||||
|
||||
fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * LCD_BPP / 8
|
||||
+ ACTIVE_VIDEO_MEM_OFFSET;
|
||||
|
||||
fbinfo->fix.line_length = fbinfo->var.xres_virtual *
|
||||
fbinfo->var.bits_per_pixel / 8;
|
||||
|
||||
|
||||
fbinfo->fbops = &bfin_lq035q1_fb_ops;
|
||||
fbinfo->flags = FBINFO_FLAG_DEFAULT;
|
||||
|
||||
info->fb_buffer =
|
||||
dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle,
|
||||
GFP_KERNEL);
|
||||
|
||||
if (NULL == info->fb_buffer) {
|
||||
dev_err(&pdev->dev, "couldn't allocate dma buffer\n");
|
||||
ret = -ENOMEM;
|
||||
goto out3;
|
||||
}
|
||||
|
||||
fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
|
||||
|
||||
fbinfo->fbops = &bfin_lq035q1_fb_ops;
|
||||
|
||||
fbinfo->pseudo_palette = &info->pseudo_pal;
|
||||
|
||||
ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n",
|
||||
BFIN_LCD_NBR_PALETTE_ENTRIES);
|
||||
goto out4;
|
||||
}
|
||||
|
||||
ret = bfin_lq035q1_request_ports(pdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "couldn't request gpio port\n");
|
||||
goto out6;
|
||||
}
|
||||
|
||||
info->irq = platform_get_irq(pdev, 0);
|
||||
if (info->irq < 0) {
|
||||
ret = -EINVAL;
|
||||
goto out7;
|
||||
}
|
||||
|
||||
ret = request_irq(info->irq, bfin_lq035q1_irq_error, IRQF_DISABLED,
|
||||
DRIVER_NAME" PPI ERROR", info);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n");
|
||||
goto out7;
|
||||
}
|
||||
|
||||
info->spidrv.driver.name = DRIVER_NAME"-spi";
|
||||
info->spidrv.probe = lq035q1_spidev_probe;
|
||||
info->spidrv.remove = __devexit_p(lq035q1_spidev_remove);
|
||||
info->spidrv.shutdown = lq035q1_spidev_shutdown;
|
||||
info->spidrv.suspend = lq035q1_spidev_suspend;
|
||||
info->spidrv.resume = lq035q1_spidev_resume;
|
||||
|
||||
ret = spi_register_driver(&info->spidrv);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "couldn't register SPI Interface\n");
|
||||
goto out8;
|
||||
}
|
||||
|
||||
if (info->disp_info->use_bl) {
|
||||
ret = gpio_request(info->disp_info->gpio_bl, "LQ035 Backlight");
|
||||
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request GPIO %d\n",
|
||||
info->disp_info->gpio_bl);
|
||||
goto out9;
|
||||
}
|
||||
gpio_direction_output(info->disp_info->gpio_bl, 0);
|
||||
}
|
||||
|
||||
ret = register_framebuffer(fbinfo);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "unable to register framebuffer\n");
|
||||
goto out10;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n",
|
||||
LCD_X_RES, LCD_Y_RES, LCD_BPP);
|
||||
|
||||
return 0;
|
||||
|
||||
out10:
|
||||
if (info->disp_info->use_bl)
|
||||
gpio_free(info->disp_info->gpio_bl);
|
||||
out9:
|
||||
spi_unregister_driver(&info->spidrv);
|
||||
out8:
|
||||
free_irq(info->irq, info);
|
||||
out7:
|
||||
bfin_lq035q1_free_ports();
|
||||
out6:
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
out4:
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
out3:
|
||||
framebuffer_release(fbinfo);
|
||||
out2:
|
||||
free_dma(CH_PPI);
|
||||
out1:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit bfin_lq035q1_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct fb_info *fbinfo = platform_get_drvdata(pdev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->disp_info->use_bl)
|
||||
gpio_free(info->disp_info->gpio_bl);
|
||||
|
||||
spi_unregister_driver(&info->spidrv);
|
||||
|
||||
unregister_framebuffer(fbinfo);
|
||||
|
||||
free_dma(CH_PPI);
|
||||
free_irq(info->irq, info);
|
||||
|
||||
if (info->fb_buffer != NULL)
|
||||
dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer,
|
||||
info->dma_handle);
|
||||
|
||||
fb_dealloc_cmap(&fbinfo->cmap);
|
||||
|
||||
bfin_lq035q1_free_ports();
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
framebuffer_release(fbinfo);
|
||||
|
||||
dev_info(&pdev->dev, "unregistered LCD driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int bfin_lq035q1_suspend(struct device *dev)
|
||||
{
|
||||
struct fb_info *fbinfo = dev_get_drvdata(dev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->lq035_open_cnt) {
|
||||
lq035q1_backlight(info, 0);
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
disable_dma(CH_PPI);
|
||||
bfin_lq035q1_stop_timers();
|
||||
bfin_write_PPI_STATUS(-1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_lq035q1_resume(struct device *dev)
|
||||
{
|
||||
struct fb_info *fbinfo = dev_get_drvdata(dev);
|
||||
struct bfin_lq035q1fb_info *info = fbinfo->par;
|
||||
|
||||
if (info->lq035_open_cnt) {
|
||||
bfin_lq035q1_disable_ppi();
|
||||
SSYNC();
|
||||
|
||||
bfin_lq035q1_config_dma(info);
|
||||
bfin_lq035q1_config_ppi(info);
|
||||
bfin_lq035q1_init_timers();
|
||||
|
||||
/* start dma */
|
||||
enable_dma(CH_PPI);
|
||||
bfin_lq035q1_enable_ppi();
|
||||
bfin_lq035q1_start_timers();
|
||||
lq035q1_backlight(info, 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dev_pm_ops bfin_lq035q1_dev_pm_ops = {
|
||||
.suspend = bfin_lq035q1_suspend,
|
||||
.resume = bfin_lq035q1_resume,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct platform_driver bfin_lq035q1_driver = {
|
||||
.probe = bfin_lq035q1_probe,
|
||||
.remove = __devexit_p(bfin_lq035q1_remove),
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &bfin_lq035q1_dev_pm_ops,
|
||||
#endif
|
||||
},
|
||||
};
|
||||
|
||||
static int __init bfin_lq035q1_driver_init(void)
|
||||
{
|
||||
return platform_driver_register(&bfin_lq035q1_driver);
|
||||
}
|
||||
module_init(bfin_lq035q1_driver_init);
|
||||
|
||||
static void __exit bfin_lq035q1_driver_cleanup(void)
|
||||
{
|
||||
platform_driver_unregister(&bfin_lq035q1_driver);
|
||||
}
|
||||
module_exit(bfin_lq035q1_driver_cleanup);
|
||||
|
||||
MODULE_DESCRIPTION("Blackfin TFT LCD Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue