ARM: hisi: enable MCPM implementation
Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM
framework to manage power on HiP04 SoC.
Changelog:
v20:
* Disable L2 prefetch when the whole cluster is down.
* Move disabling snoop filter into power_down() after L2 prefetch
disabled.
* Remove delay in wait_for_power_down() after L2 prefetch disabled.
* Add the sleep polling in wait_for_power_down() again since we
need to wait L2 when the cluster is down.
v19:
* Add comments on those delay hacks.
* Update on checking core enabled counts in wait_for_power_down().
v18:
* Fix to release resource in probe().
* Check whether cpu is already up in the process of making cpu down.
* Add udelay in power up/down sequence.
* Optimize on setting relocation entry.
* Optimize on polling status in wait_for_power_down().
* Add mcpm critical operations.
v17:
* Parse bootwrapper parameters in DTS file.
* Fix to use msleep() in spinlock region.
v16:
* Parse bootwrapper parameters in command line instead.
v13:
* Restore power down operation in MCPM.
* Fix disabling snoop filter issue in MCPM.
v12:
* Use wfi as power down state in MCPM.
* Remove wait_for_powerdown() in MCPM because wfi is used now.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Haojian Zhuang
Wei Xu
parent
ebf4a5c5b4
commit
9cdc99919a
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@ -3,4 +3,5 @@
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#
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obj-y += hisilicon.o
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obj-$(CONFIG_MCPM) += platmcpm.o
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obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
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@ -0,0 +1,386 @@
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/*
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* Copyright (c) 2013-2014 Linaro Ltd.
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* Copyright (c) 2013-2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <linux/of_address.h>
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#include <asm/cputype.h>
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#include <asm/cp15.h>
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#include <asm/mcpm.h>
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#include "core.h"
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/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x]
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* 1 -- unreset; 0 -- reset
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*/
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#define CORE_RESET_BIT(x) (1 << x)
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#define NEON_RESET_BIT(x) (1 << (x + 4))
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#define CORE_DEBUG_RESET_BIT(x) (1 << (x + 9))
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#define CLUSTER_L2_RESET_BIT (1 << 8)
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#define CLUSTER_DEBUG_RESET_BIT (1 << 13)
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/*
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* bits definition in SC_CPU_RESET_STATUS[x]
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* 1 -- reset status; 0 -- unreset status
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*/
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#define CORE_RESET_STATUS(x) (1 << x)
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#define NEON_RESET_STATUS(x) (1 << (x + 4))
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#define CORE_DEBUG_RESET_STATUS(x) (1 << (x + 9))
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#define CLUSTER_L2_RESET_STATUS (1 << 8)
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#define CLUSTER_DEBUG_RESET_STATUS (1 << 13)
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#define CORE_WFI_STATUS(x) (1 << (x + 16))
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#define CORE_WFE_STATUS(x) (1 << (x + 20))
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#define CORE_DEBUG_ACK(x) (1 << (x + 24))
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#define SC_CPU_RESET_REQ(x) (0x520 + (x << 3)) /* reset */
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#define SC_CPU_RESET_DREQ(x) (0x524 + (x << 3)) /* unreset */
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#define SC_CPU_RESET_STATUS(x) (0x1520 + (x << 3))
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#define FAB_SF_MODE 0x0c
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#define FAB_SF_INVLD 0x10
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/* bits definition in FB_SF_INVLD */
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#define FB_SF_INVLD_START (1 << 8)
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#define HIP04_MAX_CLUSTERS 4
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#define HIP04_MAX_CPUS_PER_CLUSTER 4
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#define POLL_MSEC 10
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#define TIMEOUT_MSEC 1000
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static void __iomem *sysctrl, *fabric;
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static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
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static DEFINE_SPINLOCK(boot_lock);
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static u32 fabric_phys_addr;
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/*
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* [0]: bootwrapper physical address
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* [1]: bootwrapper size
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* [2]: relocation address
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* [3]: relocation size
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*/
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static u32 hip04_boot_method[4];
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static bool hip04_cluster_is_down(unsigned int cluster)
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{
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int i;
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for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++)
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if (hip04_cpu_table[cluster][i])
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return false;
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return true;
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}
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static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on)
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{
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unsigned long data;
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if (!fabric)
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BUG();
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data = readl_relaxed(fabric + FAB_SF_MODE);
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if (on)
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data |= 1 << cluster;
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else
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data &= ~(1 << cluster);
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writel_relaxed(data, fabric + FAB_SF_MODE);
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do {
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cpu_relax();
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} while (data != readl_relaxed(fabric + FAB_SF_MODE));
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}
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static int hip04_mcpm_power_up(unsigned int cpu, unsigned int cluster)
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{
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unsigned long data;
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void __iomem *sys_dreq, *sys_status;
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if (!sysctrl)
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return -ENODEV;
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if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
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return -EINVAL;
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spin_lock_irq(&boot_lock);
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if (hip04_cpu_table[cluster][cpu])
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goto out;
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sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster);
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sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster);
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if (hip04_cluster_is_down(cluster)) {
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data = CLUSTER_DEBUG_RESET_BIT;
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writel_relaxed(data, sys_dreq);
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do {
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cpu_relax();
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data = readl_relaxed(sys_status);
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} while (data & CLUSTER_DEBUG_RESET_STATUS);
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}
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data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
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CORE_DEBUG_RESET_BIT(cpu);
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writel_relaxed(data, sys_dreq);
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do {
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cpu_relax();
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} while (data == readl_relaxed(sys_status));
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/*
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* We may fail to power up core again without this delay.
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* It's not mentioned in document. It's found by test.
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*/
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udelay(20);
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out:
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hip04_cpu_table[cluster][cpu]++;
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spin_unlock_irq(&boot_lock);
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return 0;
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}
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static void hip04_mcpm_power_down(void)
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{
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unsigned int mpidr, cpu, cluster;
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bool skip_wfi = false, last_man = false;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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__mcpm_cpu_going_down(cpu, cluster);
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spin_lock(&boot_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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hip04_cpu_table[cluster][cpu]--;
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if (hip04_cpu_table[cluster][cpu] == 1) {
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/* A power_up request went ahead of us. */
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skip_wfi = true;
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} else if (hip04_cpu_table[cluster][cpu] > 1) {
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pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
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BUG();
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}
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last_man = hip04_cluster_is_down(cluster);
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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spin_unlock(&boot_lock);
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/* Since it's Cortex A15, disable L2 prefetching. */
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3 \n\t"
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"isb \n\t"
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"dsb "
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: : "r" (0x400) );
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v7_exit_coherency_flush(all);
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hip04_set_snoop_filter(cluster, 0);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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spin_unlock(&boot_lock);
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v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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if (!skip_wfi)
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wfi();
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}
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static int hip04_mcpm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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{
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unsigned int data, tries, count;
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int ret = -ETIMEDOUT;
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BUG_ON(cluster >= HIP04_MAX_CLUSTERS ||
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cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
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count = TIMEOUT_MSEC / POLL_MSEC;
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spin_lock_irq(&boot_lock);
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for (tries = 0; tries < count; tries++) {
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if (hip04_cpu_table[cluster][cpu]) {
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ret = -EBUSY;
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goto err;
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}
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cpu_relax();
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data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
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if (data & CORE_WFI_STATUS(cpu))
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break;
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spin_unlock_irq(&boot_lock);
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/* Wait for clean L2 when the whole cluster is down. */
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msleep(POLL_MSEC);
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spin_lock_irq(&boot_lock);
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}
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if (tries >= count)
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goto err;
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data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \
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CORE_DEBUG_RESET_BIT(cpu);
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writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster));
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for (tries = 0; tries < count; tries++) {
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cpu_relax();
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data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
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if (data & CORE_RESET_STATUS(cpu))
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break;
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}
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if (tries >= count)
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goto err;
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spin_unlock_irq(&boot_lock);
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return 0;
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err:
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spin_unlock_irq(&boot_lock);
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return ret;
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}
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static void hip04_mcpm_powered_up(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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spin_lock(&boot_lock);
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if (!hip04_cpu_table[cluster][cpu])
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hip04_cpu_table[cluster][cpu] = 1;
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spin_unlock(&boot_lock);
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}
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static void __naked hip04_mcpm_power_up_setup(unsigned int affinity_level)
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{
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asm volatile (" \n"
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" cmp r0, #0 \n"
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" bxeq lr \n"
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/* calculate fabric phys address */
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" adr r2, 2f \n"
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" ldmia r2, {r1, r3} \n"
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" sub r0, r2, r1 \n"
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" ldr r2, [r0, r3] \n"
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/* get cluster id from MPIDR */
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" mrc p15, 0, r0, c0, c0, 5 \n"
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" ubfx r1, r0, #8, #8 \n"
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/* 1 << cluster id */
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" mov r0, #1 \n"
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" mov r3, r0, lsl r1 \n"
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" ldr r0, [r2, #"__stringify(FAB_SF_MODE)"] \n"
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" tst r0, r3 \n"
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" bxne lr \n"
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" orr r1, r0, r3 \n"
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" str r1, [r2, #"__stringify(FAB_SF_MODE)"] \n"
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"1: ldr r0, [r2, #"__stringify(FAB_SF_MODE)"] \n"
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" tst r0, r3 \n"
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" beq 1b \n"
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" bx lr \n"
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" .align 2 \n"
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"2: .word . \n"
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" .word fabric_phys_addr \n"
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);
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}
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static const struct mcpm_platform_ops hip04_mcpm_ops = {
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.power_up = hip04_mcpm_power_up,
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.power_down = hip04_mcpm_power_down,
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.wait_for_powerdown = hip04_mcpm_wait_for_powerdown,
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.powered_up = hip04_mcpm_powered_up,
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};
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static bool __init hip04_cpu_table_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (cluster >= HIP04_MAX_CLUSTERS ||
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cpu >= HIP04_MAX_CPUS_PER_CLUSTER) {
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pr_err("%s: boot CPU is out of bound!\n", __func__);
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return false;
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}
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hip04_set_snoop_filter(cluster, 1);
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hip04_cpu_table[cluster][cpu] = 1;
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return true;
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}
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static int __init hip04_mcpm_init(void)
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{
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struct device_node *np, *np_sctl, *np_fab;
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struct resource fab_res;
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void __iomem *relocation;
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int ret = -ENODEV;
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np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper");
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if (!np)
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goto err;
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ret = of_property_read_u32_array(np, "boot-method",
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&hip04_boot_method[0], 4);
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if (ret)
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goto err;
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np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
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if (!np_sctl)
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goto err;
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np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric");
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if (!np_fab)
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goto err;
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ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]);
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if (ret)
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goto err;
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relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]);
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if (!relocation) {
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pr_err("failed to map relocation space\n");
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ret = -ENOMEM;
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goto err_reloc;
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}
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sysctrl = of_iomap(np_sctl, 0);
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if (!sysctrl) {
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pr_err("failed to get sysctrl base\n");
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ret = -ENOMEM;
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goto err_sysctrl;
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}
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ret = of_address_to_resource(np_fab, 0, &fab_res);
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if (ret) {
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pr_err("failed to get fabric base phys\n");
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goto err_fabric;
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}
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fabric_phys_addr = fab_res.start;
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sync_cache_w(&fabric_phys_addr);
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fabric = of_iomap(np_fab, 0);
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if (!fabric) {
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pr_err("failed to get fabric base\n");
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ret = -ENOMEM;
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goto err_fabric;
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}
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if (!hip04_cpu_table_init()) {
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ret = -EINVAL;
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goto err_table;
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}
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ret = mcpm_platform_register(&hip04_mcpm_ops);
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if (ret) {
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goto err_table;
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}
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/*
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* Fill the instruction address that is used after secondary core
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* out of reset.
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*/
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writel_relaxed(hip04_boot_method[0], relocation);
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writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */
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writel_relaxed(virt_to_phys(mcpm_entry_point), relocation + 8);
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writel_relaxed(0, relocation + 12);
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iounmap(relocation);
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mcpm_sync_init(hip04_mcpm_power_up_setup);
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mcpm_smp_set_ops();
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pr_info("HiP04 MCPM initialized\n");
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return ret;
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err_table:
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iounmap(fabric);
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err_fabric:
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iounmap(sysctrl);
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err_sysctrl:
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iounmap(relocation);
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err_reloc:
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memblock_free(hip04_boot_method[0], hip04_boot_method[1]);
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err:
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return ret;
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}
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early_initcall(hip04_mcpm_init);
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