clock-imx35: fix reboot in internal boot mode
commit 8d75a26
"ARM: mx35: use generic function for displaying silicon revision"
disabled IIM clock after reading silicon revision which will prevent
reboot in internal boot mode.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Cc: Jason Liu <jason.hui@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -507,7 +507,7 @@ static struct clk_lookup lookups[] = {
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int __init mx35_clocks_init()
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{
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unsigned int cgr2 = 3 << 26, cgr3 = 0;
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unsigned int cgr2 = 3 << 26;
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#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
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cgr2 |= 3 << 16;
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@ -521,6 +521,12 @@ int __init mx35_clocks_init()
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__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
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__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
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CCM_BASE + CCM_CGR1);
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__raw_writel(cgr2, CCM_BASE + CCM_CGR2);
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__raw_writel(0, CCM_BASE + CCM_CGR3);
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clk_enable(&iim_clk);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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clk_disable(&iim_clk);
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/*
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* Check if we came up in internal boot mode. If yes, we need some
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@ -529,17 +535,11 @@ int __init mx35_clocks_init()
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*/
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if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
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/* Additionally turn on UART1, SCC, and IIM clocks */
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cgr2 |= 3 << 16 | 3 << 4;
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cgr3 |= 3 << 2;
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clk_enable(&iim_clk);
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clk_enable(&uart1_clk);
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clk_enable(&scc_clk);
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}
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__raw_writel(cgr2, CCM_BASE + CCM_CGR2);
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__raw_writel(cgr3, CCM_BASE + CCM_CGR3);
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clk_enable(&iim_clk);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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clk_disable(&iim_clk);
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#ifdef CONFIG_MXC_USE_EPIT
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epit_timer_init(&epit1_clk,
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MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
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