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drm/amd/display: Fix updating infoframe for DCN3.1 eDP 

[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.

[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2021-06-16 17:11:12 -04:00 committed by Alex Deucher
parent 46db138dc8
commit 9cb2f2df66
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
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@ -390,7 +390,7 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
if (!is_hdmi_tmds)
if (!is_hdmi_tmds && !is_dp)
return;
if (is_hdmi_tmds)