net: mvpp2: add TX FC firmware check

Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Acked-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Stefan Chulski 2021-02-11 12:49:02 +02:00 committed by David S. Miller
parent 262412d55a
commit 9ca5e767ec
2 changed files with 33 additions and 7 deletions

View File

@ -828,6 +828,7 @@
#define MSS_THRESHOLD_STOP 768
#define MSS_THRESHOLD_START 1024
#define MSS_FC_MAX_TIMEOUT 5000
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \

View File

@ -924,6 +924,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
}
static int mvpp2_enable_global_fc(struct mvpp2 *priv)
{
int val, timeout = 0;
/* Enable global flow control. In this stage global
* flow control enabled, but still disabled per port.
*/
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
val |= FLOW_CONTROL_ENABLE_BIT;
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
/* Check if Firmware running and disable FC if not*/
val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
while (timeout < MSS_FC_MAX_TIMEOUT) {
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
return 0;
usleep_range(10, 20);
timeout++;
}
priv->global_tx_fc = false;
return -EOPNOTSUPP;
}
/* Release buffer to BM */
static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
dma_addr_t buf_dma_addr,
@ -7264,7 +7292,7 @@ static int mvpp2_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *base;
int i, shared;
int err, val;
int err;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@ -7488,13 +7516,10 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_port_probe;
}
/* Enable global flow control. In this stage global
* flow control enabled, but still disabled per port.
*/
if (priv->global_tx_fc && priv->hw_version != MVPP21) {
val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
val |= FLOW_CONTROL_ENABLE_BIT;
mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
err = mvpp2_enable_global_fc(priv);
if (err)
dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
}
mvpp2_dbgfs_init(priv, pdev->name);