net: mvpp2: add TX FC firmware check
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -828,6 +828,7 @@
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#define MSS_THRESHOLD_STOP 768
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#define MSS_THRESHOLD_START 1024
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#define MSS_FC_MAX_TIMEOUT 5000
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/* RX buffer constants */
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#define MVPP2_SKB_SHINFO_SIZE \
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@ -924,6 +924,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
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spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
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}
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static int mvpp2_enable_global_fc(struct mvpp2 *priv)
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{
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int val, timeout = 0;
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/* Enable global flow control. In this stage global
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* flow control enabled, but still disabled per port.
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*/
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val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
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val |= FLOW_CONTROL_ENABLE_BIT;
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mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
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/* Check if Firmware running and disable FC if not*/
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val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
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mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
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while (timeout < MSS_FC_MAX_TIMEOUT) {
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val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
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if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
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return 0;
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usleep_range(10, 20);
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timeout++;
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}
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priv->global_tx_fc = false;
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return -EOPNOTSUPP;
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}
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/* Release buffer to BM */
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static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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dma_addr_t buf_dma_addr,
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@ -7264,7 +7292,7 @@ static int mvpp2_probe(struct platform_device *pdev)
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struct resource *res;
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void __iomem *base;
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int i, shared;
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int err, val;
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int err;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@ -7488,13 +7516,10 @@ static int mvpp2_probe(struct platform_device *pdev)
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goto err_port_probe;
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}
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/* Enable global flow control. In this stage global
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* flow control enabled, but still disabled per port.
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*/
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if (priv->global_tx_fc && priv->hw_version != MVPP21) {
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val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
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val |= FLOW_CONTROL_ENABLE_BIT;
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mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
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err = mvpp2_enable_global_fc(priv);
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if (err)
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dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
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}
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mvpp2_dbgfs_init(priv, pdev->name);
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