UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

arm64: dts: xilinx: Add the clock nodes for zynqmp 

Add clock nodes for zynqmp based on CCF.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Rajan Vaja 2019-11-07 01:44:14 -08:00 committed by Michal Simek
parent df906cf54b
commit 9c8a47b484
15 changed files with 265 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

222
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi Normal file
View File

@ -0,0 +1,222 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
pss_ref_clk: pss_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
video_clk: video_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
pss_alt_ref_clk: pss_alt_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gt_crx_ref_clk: gt_crx_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
};
aux_ref_clk: aux_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&can1 {
clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&cpu0 {
clocks = <&zynqmp_clk ACPU>;
};
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan2 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan3 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan4 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan5 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan6 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan7 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan8 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan2 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan3 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan4 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan5 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan6 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan7 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan8 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gem0 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gpio {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&i2c0 {
clocks = <&zynqmp_clk I2C0_REF>;
};
&i2c1 {
clocks = <&zynqmp_clk I2C1_REF>;
};
&pcie {
clocks = <&zynqmp_clk PCIE_REF>;
};
&sata {
clocks = <&zynqmp_clk SATA_REF>;
};
&sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi0 {
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi1 {
clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&ttc0 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc1 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc2 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc3 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1232 RevA";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1254 RevA";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy
@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

18
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2015, Xilinx, Inc.
* (C) Copyright 2014 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
@ -120,6 +120,22 @@
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_clk: clock-controller {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>,
<&video_clk>,
<&pss_alt_ref_clk>,
<&aux_ref_clk>,
<&gt_crx_ref_clk>;
clock-names = "pss_ref_clk",
"video_clk",
"pss_alt_ref_clk",
"aux_ref_clk",
"gt_crx_ref_clk";
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;