ARM64: DT: Hisilicon SoCs DT updates for 5.8
- Add pinconf for spi2 and spi3 nodes and increase the drive strength to achieve the max speed for the Hikey960 board - Add CTI nodes for the Hikey620 board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJevjyIAAoJEAvIV27ZiWZcGoYQAJdLtw+VmW+NarmObzZ1vFh9 tpAWA1UDgH6oY61lscdbi8feAYmj2i8kdCCEFldxUSQCcVFX3MoZAJMTb18EaASg tJpLvHcNd47BYv+t9VdlIcEsbKHmZO1eJU4KnzOR4uHr6sS1n4spwpPV7lhIFoHY yp5xZSp5COraHrmBkytgcLgxMhLmQl40Kej1MF2Ce6bP/+C10UuejPOn8KaO9bmm +7ipF0B254HxmzJJlNWszVJiBweX8UYmeSAe/xLz5mbKAHYnZ1R9Iz2+lJO8SQSz ztPrZ5JRW+FNGbHq+Q+e5l2OdxcVoIptlHLbrrmVCt7NoTm/CeXnOg7SzxfHN8J9 Y8GyFugjXRV4Oe/3SzlApy4Yq5Hf3iAi0jNrbwQHasKptOXEIP/XLP+slppbQmPY aklo8iIxM9rUuqHoolFmvl+KE8B7v12YkhBa0sQXWwbGNW2jF6cBknHRC/Lrq6/a W0VDdAQJ+Tu8fLvG2mO71ZGAvSC0FMkkQ1XE6wMKNkbwf4g1DCgkK+EqQV1eeZcz WJfgwyMQcql6uv5ICbvgiL48MrAxDCaxMLvvjZc1ti9e2DDMROXILCR5Z/tKd8UB +2ve/5xcVdujClfpPUoAPwKGrRG9cKZ4PuNOfw5YGntFvLBwhXjtLCjf3/hF4dbD Qt9KY+9bBMDcf3qY4JrX =+heh -----END PGP SIGNATURE----- Merge tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi into arm/dt ARM64: DT: Hisilicon SoCs DT updates for 5.8 - Add pinconf for spi2 and spi3 nodes and increase the drive strength to achieve the max speed for the Hikey960 board - Add CTI nodes for the Hikey620 board * tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi6220: Add CTI options arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf Link: https://lore.kernel.org/r/5EBE430E.6090508@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9c7ae8edb9
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@ -974,7 +974,7 @@
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clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
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clock-names = "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_pmx_func>;
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pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
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num-cs = <1>;
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cs-gpios = <&gpio27 2 0>;
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status = "disabled";
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@ -989,7 +989,7 @@
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clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
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clock-names = "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&spi3_pmx_func>;
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pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
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num-cs = <1>;
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cs-gpios = <&gpio18 5 0>;
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status = "disabled";
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@ -213,7 +213,7 @@
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};
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};
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etm@f659c000 {
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etm0: etm@f659c000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659c000 0 0x1000>;
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@ -232,7 +232,7 @@
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};
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};
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etm@f659d000 {
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etm1: etm@f659d000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659d000 0 0x1000>;
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@ -251,7 +251,7 @@
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};
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};
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etm@f659e000 {
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etm2: etm@f659e000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659e000 0 0x1000>;
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@ -270,7 +270,7 @@
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};
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};
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etm@f659f000 {
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etm3: etm@f659f000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659f000 0 0x1000>;
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@ -289,7 +289,7 @@
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};
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};
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etm@f65dc000 {
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etm4: etm@f65dc000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dc000 0 0x1000>;
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@ -308,7 +308,7 @@
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};
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};
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etm@f65dd000 {
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etm5: etm@f65dd000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dd000 0 0x1000>;
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@ -327,7 +327,7 @@
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};
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};
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etm@f65de000 {
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etm6: etm@f65de000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65de000 0 0x1000>;
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@ -346,7 +346,7 @@
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};
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};
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etm@f65df000 {
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etm7: etm@f65df000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65df000 0 0x1000>;
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@ -364,5 +364,119 @@
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};
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};
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};
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/* System CTIs */
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/* CTI 0 - TMC and TPIU connections */
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cti@f6403000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6403000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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};
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/* CTI - CPU-0 */
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cti@f6598000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6598000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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arm,cs-dev-assoc = <&etm0>;
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};
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/* CTI - CPU-1 */
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cti@f6599000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6599000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu1>;
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arm,cs-dev-assoc = <&etm1>;
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};
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/* CTI - CPU-2 */
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cti@f659a000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf659a000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu2>;
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arm,cs-dev-assoc = <&etm2>;
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};
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/* CTI - CPU-3 */
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cti@f659b000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf659b000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu3>;
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arm,cs-dev-assoc = <&etm3>;
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};
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/* CTI - CPU-4 */
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cti@f65d8000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65d8000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu4>;
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arm,cs-dev-assoc = <&etm4>;
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};
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/* CTI - CPU-5 */
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cti@f65d9000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65d9000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu5>;
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arm,cs-dev-assoc = <&etm5>;
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};
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/* CTI - CPU-6 */
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cti@f65da000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65da000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu6>;
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arm,cs-dev-assoc = <&etm6>;
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};
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/* CTI - CPU-7 */
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cti@f65db000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65db000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu7>;
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arm,cs-dev-assoc = <&etm7>;
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};
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};
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};
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@ -717,7 +717,7 @@
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spi3_cfg_func: spi3_cfg_func {
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pinctrl-single,pins = <
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0x008 0x0 /* SPI3_CLK */
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0x0 /* SPI3_DI */
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0x00c 0x0 /* SPI3_DI */
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0x010 0x0 /* SPI3_DO */
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0x014 0x0 /* SPI3_CS0_N */
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>;
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@ -734,7 +734,7 @@
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_02MA DRIVE6_MASK
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DRIVE7_06MA DRIVE6_MASK
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>;
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};
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};
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@ -1031,7 +1031,7 @@
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PULL_UP
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>;
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pinctrl-single,drive-strength = <
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DRIVE7_02MA DRIVE6_MASK
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DRIVE7_06MA DRIVE6_MASK
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>;
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};
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