Merge tag 'amd-drm-fixes-5.12-2021-02-24' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-fixes-5.12-2021-02-24: amdgpu: - Clang warning fix - S0ix platform shutdown/poweroff fix - Misc display fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210225043853.3880-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
9c712c9c38
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@ -1008,6 +1008,12 @@ struct amdgpu_device {
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bool in_suspend;
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bool in_hibernate;
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/*
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* The combination flag in_poweroff_reboot_com used to identify the poweroff
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* and reboot opt in the s0i3 system-wide suspend.
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*/
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bool in_poweroff_reboot_com;
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atomic_t in_gpu_reset;
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enum pp_mp1_state mp1_state;
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struct rw_semaphore reset_sem;
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@ -2678,7 +2678,8 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
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{
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int i, r;
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if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
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if (adev->in_poweroff_reboot_com ||
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!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) {
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
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}
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@ -3741,7 +3742,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
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amdgpu_fence_driver_suspend(adev);
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if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
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if (adev->in_poweroff_reboot_com ||
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!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev))
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r = amdgpu_device_ip_suspend_phase2(adev);
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else
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amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
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@ -1270,7 +1270,9 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
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*/
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if (!amdgpu_passthrough(adev))
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adev->mp1_state = PP_MP1_STATE_UNLOAD;
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adev->in_poweroff_reboot_com = true;
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amdgpu_device_ip_suspend(adev);
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adev->in_poweroff_reboot_com = false;
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adev->mp1_state = PP_MP1_STATE_NONE;
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}
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@ -1312,8 +1314,13 @@ static int amdgpu_pmops_thaw(struct device *dev)
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static int amdgpu_pmops_poweroff(struct device *dev)
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{
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struct drm_device *drm_dev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = drm_to_adev(drm_dev);
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int r;
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return amdgpu_device_suspend(drm_dev, true);
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adev->in_poweroff_reboot_com = true;
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r = amdgpu_device_suspend(drm_dev, true);
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adev->in_poweroff_reboot_com = false;
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return r;
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}
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static int amdgpu_pmops_restore(struct device *dev)
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@ -937,7 +937,49 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
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}
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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static void event_mall_stutter(struct work_struct *work)
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{
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struct vblank_workqueue *vblank_work = container_of(work, struct vblank_workqueue, mall_work);
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struct amdgpu_display_manager *dm = vblank_work->dm;
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mutex_lock(&dm->dc_lock);
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if (vblank_work->enable)
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dm->active_vblank_irq_count++;
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else
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dm->active_vblank_irq_count--;
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dc_allow_idle_optimizations(
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dm->dc, dm->active_vblank_irq_count == 0 ? true : false);
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DRM_DEBUG_DRIVER("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
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mutex_unlock(&dm->dc_lock);
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}
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static struct vblank_workqueue *vblank_create_workqueue(struct amdgpu_device *adev, struct dc *dc)
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{
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int max_caps = dc->caps.max_links;
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struct vblank_workqueue *vblank_work;
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int i = 0;
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vblank_work = kcalloc(max_caps, sizeof(*vblank_work), GFP_KERNEL);
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if (ZERO_OR_NULL_PTR(vblank_work)) {
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kfree(vblank_work);
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return NULL;
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}
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for (i = 0; i < max_caps; i++)
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INIT_WORK(&vblank_work[i].mall_work, event_mall_stutter);
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return vblank_work;
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}
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#endif
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static int amdgpu_dm_init(struct amdgpu_device *adev)
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{
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struct dc_init_data init_data;
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@ -957,6 +999,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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mutex_init(&adev->dm.dc_lock);
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mutex_init(&adev->dm.audio_lock);
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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spin_lock_init(&adev->dm.vblank_lock);
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#endif
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if(amdgpu_dm_irq_init(adev)) {
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DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
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@ -1071,6 +1116,17 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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amdgpu_dm_init_color_mod();
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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if (adev->dm.dc->caps.max_links > 0) {
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adev->dm.vblank_workqueue = vblank_create_workqueue(adev, adev->dm.dc);
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if (!adev->dm.vblank_workqueue)
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DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
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else
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DRM_DEBUG_DRIVER("amdgpu: vblank_workqueue init done %p.\n", adev->dm.vblank_workqueue);
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}
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#endif
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
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adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
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@ -1936,7 +1992,7 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
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dc_commit_updates_for_stream(
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dm->dc, bundle->surface_updates,
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dc_state->stream_status->plane_count,
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dc_state->streams[k], &bundle->stream_update);
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dc_state->streams[k], &bundle->stream_update, dc_state);
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}
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cleanup:
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@ -1967,7 +2023,8 @@ static void dm_set_dpms_off(struct dc_link *link)
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stream_update.stream = stream_state;
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dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
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stream_state, &stream_update);
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stream_state, &stream_update,
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stream_state->ctx->dc->current_state);
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mutex_unlock(&adev->dm.dc_lock);
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}
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@ -5374,7 +5431,10 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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struct amdgpu_device *adev = drm_to_adev(crtc->dev);
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struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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struct amdgpu_display_manager *dm = &adev->dm;
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unsigned long flags;
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#endif
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int rc = 0;
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if (enable) {
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@ -5397,22 +5457,15 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
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if (amdgpu_in_reset(adev))
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return 0;
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mutex_lock(&dm->dc_lock);
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if (enable)
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dm->active_vblank_irq_count++;
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else
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dm->active_vblank_irq_count--;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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dc_allow_idle_optimizations(
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adev->dm.dc, dm->active_vblank_irq_count == 0 ? true : false);
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DRM_DEBUG_DRIVER("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
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spin_lock_irqsave(&dm->vblank_lock, flags);
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dm->vblank_workqueue->dm = dm;
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dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
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dm->vblank_workqueue->enable = enable;
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spin_unlock_irqrestore(&dm->vblank_lock, flags);
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schedule_work(&dm->vblank_workqueue->mall_work);
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#endif
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mutex_unlock(&dm->dc_lock);
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return 0;
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}
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@ -7663,7 +7716,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct drm_crtc *pcrtc,
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bool wait_for_vblank)
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{
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int i;
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uint32_t i;
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uint64_t timestamp_ns;
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struct drm_plane *plane;
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struct drm_plane_state *old_plane_state, *new_plane_state;
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@ -7704,7 +7757,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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amdgpu_dm_commit_cursors(state);
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/* update planes when needed */
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
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struct drm_crtc *crtc = new_plane_state->crtc;
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struct drm_crtc_state *new_crtc_state;
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struct drm_framebuffer *fb = new_plane_state->fb;
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@ -7927,7 +7980,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->surface_updates,
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planes_count,
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acrtc_state->stream,
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&bundle->stream_update);
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&bundle->stream_update,
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dc_state);
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/**
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* Enable or disable the interrupts on the backend.
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@ -8263,13 +8317,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
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struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
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struct dc_surface_update surface_updates[MAX_SURFACES];
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struct dc_surface_update dummy_updates[MAX_SURFACES];
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struct dc_stream_update stream_update;
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struct dc_info_packet hdr_packet;
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struct dc_stream_status *status = NULL;
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bool abm_changed, hdr_changed, scaling_changed;
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memset(&surface_updates, 0, sizeof(surface_updates));
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memset(&dummy_updates, 0, sizeof(dummy_updates));
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memset(&stream_update, 0, sizeof(stream_update));
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if (acrtc) {
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@ -8326,15 +8380,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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* To fix this, DC should permit updating only stream properties.
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*/
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for (j = 0; j < status->plane_count; j++)
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surface_updates[j].surface = status->plane_states[j];
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dummy_updates[j].surface = status->plane_states[0];
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mutex_lock(&dm->dc_lock);
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dc_commit_updates_for_stream(dm->dc,
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surface_updates,
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dummy_updates,
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status->plane_count,
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dm_new_crtc_state->stream,
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&stream_update);
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&stream_update,
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dc_state);
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mutex_unlock(&dm->dc_lock);
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}
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@ -92,6 +92,20 @@ struct dm_compressor_info {
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uint64_t gpu_addr;
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};
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/**
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* struct vblank_workqueue - Works to be executed in a separate thread during vblank
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* @mall_work: work for mall stutter
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* @dm: amdgpu display manager device
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* @otg_inst: otg instance of which vblank is being set
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* @enable: true if enable vblank
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*/
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struct vblank_workqueue {
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struct work_struct mall_work;
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struct amdgpu_display_manager *dm;
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int otg_inst;
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bool enable;
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};
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/**
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* struct amdgpu_dm_backlight_caps - Information about backlight
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*
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@ -243,6 +257,15 @@ struct amdgpu_display_manager {
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*/
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struct mutex audio_lock;
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/**
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* @vblank_work_lock:
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*
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* Guards access to deferred vblank work state.
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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spinlock_t vblank_lock;
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#endif
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/**
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* @audio_component:
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*
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@ -321,6 +344,10 @@ struct amdgpu_display_manager {
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struct hdcp_workqueue *hdcp_workqueue;
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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struct vblank_workqueue *vblank_workqueue;
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#endif
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struct drm_atomic_state *cached_state;
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struct dc_state *cached_dc_state;
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@ -2697,7 +2697,8 @@ void dc_commit_updates_for_stream(struct dc *dc,
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struct dc_surface_update *srf_updates,
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int surface_count,
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struct dc_stream_state *stream,
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struct dc_stream_update *stream_update)
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struct dc_stream_update *stream_update,
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struct dc_state *state)
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{
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const struct dc_stream_status *stream_status;
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enum surface_update_type update_type;
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@ -2716,12 +2717,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
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if (update_type >= UPDATE_TYPE_FULL) {
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struct dc_plane_state *new_planes[MAX_SURFACES];
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memset(new_planes, 0, sizeof(new_planes));
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for (i = 0; i < surface_count; i++)
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new_planes[i] = srf_updates[i].surface;
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/* initialize scratch memory for building context */
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context = dc_create_state(dc);
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@ -2730,21 +2725,15 @@ void dc_commit_updates_for_stream(struct dc *dc,
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return;
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}
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dc_resource_state_copy_construct(
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dc->current_state, context);
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dc_resource_state_copy_construct(state, context);
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/*remove old surfaces from context */
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if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
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DC_ERROR("Failed to remove streams for new validate context!\n");
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return;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
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struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
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new_pipe->plane_state->force_full_update = true;
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}
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/* add surface to context */
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if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
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DC_ERROR("Failed to add streams for new validate context!\n");
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return;
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}
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|
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}
|
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|
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|
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|
|
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|
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@ -294,7 +294,8 @@ void dc_commit_updates_for_stream(struct dc *dc,
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struct dc_surface_update *srf_updates,
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int surface_count,
|
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struct dc_stream_state *stream,
|
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struct dc_stream_update *stream_update);
|
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struct dc_stream_update *stream_update,
|
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struct dc_state *state);
|
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/*
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* Log the current stream state.
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*/
|
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|
|
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@ -480,7 +480,6 @@ unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
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break;
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default:
|
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// invalid source select DIG
|
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ASSERT(false);
|
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result = ENGINE_ID_UNKNOWN;
|
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}
|
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|
||||
|
|
|
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|
|
@ -539,6 +539,8 @@ void dcn30_init_hw(struct dc *dc)
|
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|
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fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
|
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dc->links[i]->link_enc);
|
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if (fe == ENGINE_ID_UNKNOWN)
|
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continue;
|
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|
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for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
|
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if (fe == dc->res_pool->stream_enc[j]->id) {
|
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|
|
|
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|
|
@ -168,6 +168,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
|
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.ack = NULL
|
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};
|
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|
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static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
|
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.set = NULL,
|
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.ack = NULL
|
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};
|
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|
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#undef BASE_INNER
|
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#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
|
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|
||||
|
|
@ -230,6 +235,17 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
|
|||
.funcs = &vblank_irq_info_funcs\
|
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}
|
||||
|
||||
/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
|
||||
* of DCE's DC_IRQ_SOURCE_VUPDATEx.
|
||||
*/
|
||||
#define vupdate_no_lock_int_entry(reg_num)\
|
||||
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
|
||||
IRQ_REG_ENTRY(OTG, reg_num,\
|
||||
OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
|
||||
OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
|
||||
.funcs = &vupdate_no_lock_irq_info_funcs\
|
||||
}
|
||||
|
||||
#define vblank_int_entry(reg_num)\
|
||||
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
|
||||
IRQ_REG_ENTRY(OTG, reg_num,\
|
||||
|
|
@ -338,6 +354,12 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
|
|||
vupdate_int_entry(3),
|
||||
vupdate_int_entry(4),
|
||||
vupdate_int_entry(5),
|
||||
vupdate_no_lock_int_entry(0),
|
||||
vupdate_no_lock_int_entry(1),
|
||||
vupdate_no_lock_int_entry(2),
|
||||
vupdate_no_lock_int_entry(3),
|
||||
vupdate_no_lock_int_entry(4),
|
||||
vupdate_no_lock_int_entry(5),
|
||||
vblank_int_entry(0),
|
||||
vblank_int_entry(1),
|
||||
vblank_int_entry(2),
|
||||
|
|
|
|||
|
|
@ -762,7 +762,7 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
|
|||
structure_size = sizeof(struct gpu_metrics_v2_0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
return;
|
||||
}
|
||||
|
||||
#undef METRICS_VERSION
|
||||
|
|
|
|||
Loading…
Reference in New Issue