arm64: tegra: Device tree changes for v5.3-rc1
This contains the bulk of the Tegra changes this cycle. It has a bunch of improvements across almost all boards. These are mostly small and not too exciting additions. Most notably perhaps is the continuation of Jetson Nano support, which is now mostly on feature parity with Jetson TX1. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl0M7HYTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoeIUD/9udVMjomFq6udm5zzCazIsg7Aab3/4 ctSLRppFCsiC01BInPTTwSPh0Lv0LJ5EALvIXIDyyel9xApJ66kOCQAVqVCyPUmv exqGTsKX44EzAYA2DVJR+qFDqPG4RD37PiBPkys7q7+H+sA8mz+dBNDckv76VYP5 04xbv3rWC3NAs31i6NuiPitoSxpKBwfvguSdGS0BII8soI0yhilvqNnZp08XRdx7 0W2AlOZvqFvti7288xeQPk57LJaR6pE7rnb1B5bPJwEzl7zRnu7A20u99xVZclTx XtHVXj5c52hVO1DKQ1mUL01xiA6Q0Ru+cfhLiEjaBot4MVoDkL0djeZYWG+Z1TWq NdKOaoi1Qiwpd6YbzyCWMvurFt8ZW2QDbu8hGf/jzI6TIogcajVC9gzm82kFnfu3 1OefivyVx0WiXsTn+yIBI0NAiza5joZgh9fdX7R38l89oOx3VrQwyClJKFNSbkwV veI7UTLTZ2iKIwTwEoBaP2kO4SZKZ3/uvXdz89Pck8UooIeC9yU3aqcMZCyInXmn +MQlGiI2n5IIRbmNMKNHeece1gDzuvo9RSqzonwxNG3Zvt4J2bbfv7Q91itAJMjr mq8vNmVutfS36zgzcfbhfkPVO8hHX4OxOHWISZOtXbyCSzfY3j/HTuPRSLZBU2XZ xMFsMfefTEtcWA== =Ea0t -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.3-rc1 This contains the bulk of the Tegra changes this cycle. It has a bunch of improvements across almost all boards. These are mostly small and not too exciting additions. Most notably perhaps is the continuation of Jetson Nano support, which is now mostly on feature parity with Jetson TX1. * tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits) arm64: tegra: Enable PCIe slots in P2972-0000 board arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT arm64: tegra: Add PEX DPD states as pinctrl properties arm64: tegra: Enable ACONNECT, ADMA and AGIC arm64: tegra: Add ACONNECT, ADMA and AGIC nodes arm64: tegra: Sort device tree nodes alphabetically arm64: tegra: Fix Jetson Nano GPU regulator arm64: tegra: Update Jetson TX1 GPU regulator timings arm64: tegra: Fix AGIC register range arm64: tegra: Add INA3221 channel info for Jetson TX2 arm64: tegra: Enable PWM on Jetson Nano arm64: tegra: Enable CPU sleep on Jetson Nano arm64: tegra: Add ID EEPROMs on Jetson Nano arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit arm64: tegra: Add ID EEPROM for Jetson TX2 module arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit arm64: tegra: Add ID EEPROM for Jetson TX1 module arm64: tegra: Don't use architected timer for suspend on Tegra210 arm64: tegra: Mark architected timer as always on arm64: tegra: Add pin control states for I2C on Tegra186 ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
9c644f83ea
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@ -7,18 +7,70 @@
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#include "tegra186-p3310.dtsi"
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/ {
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model = "NVIDIA Tegra186 P2771-0000 Development Board";
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model = "NVIDIA Jetson TX2 Developer Kit";
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compatible = "nvidia,p2771-0000", "nvidia,tegra186";
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aconnect {
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status = "okay";
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dma-controller@2930000 {
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status = "okay";
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};
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interrupt-controller@2a40000 {
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status = "okay";
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};
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};
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i2c@3160000 {
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power-monitor@42 {
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compatible = "ti,ina3221";
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reg = <0x42>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_MUX";
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shunt-resistor-micro-ohms = <20000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_5V0_IO_SYS";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_3V3_SYS";
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shunt-resistor-micro-ohms = <10000>;
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};
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};
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power-monitor@43 {
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compatible = "ti,ina3221";
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reg = <0x43>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_3V3_IO_SLP";
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shunt-resistor-micro-ohms = <10000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_1V8_IO";
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shunt-resistor-micro-ohms = <10000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_M2_IN";
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shunt-resistor-micro-ohms = <10000>;
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};
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};
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exp1: gpio@74 {
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@ -31,6 +83,8 @@
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#gpio-cells = <2>;
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gpio-controller;
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vcc-supply = <&vdd_3v3_sys>;
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};
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exp2: gpio@77 {
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@ -43,6 +97,8 @@
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#gpio-cells = <2>;
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gpio-controller;
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vcc-supply = <&vdd_1v8>;
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};
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};
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@ -145,6 +201,19 @@
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phy-names = "usb2-0", "usb2-1", "usb3-0";
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};
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i2c@c250000 {
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/* carrier board ID EEPROM */
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eeprom@57 {
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compatible = "atmel,24c02";
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reg = <0x57>;
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address-bits = <8>;
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page-size = <8>;
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size = <256>;
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read-only;
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};
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};
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pcie@10003000 {
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status = "okay";
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@ -278,7 +347,7 @@
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio TEGRA_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
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gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vdd_5v0_sys>;
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@ -292,7 +361,7 @@
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio TEGRA_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
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gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vdd_5v0_sys>;
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@ -4,7 +4,7 @@
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#include <dt-bindings/mfd/max77620.h>
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/ {
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model = "NVIDIA Tegra186 P3310 Processor Module";
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model = "NVIDIA Jetson TX2";
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compatible = "nvidia,p3310", "nvidia,tegra186";
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aliases {
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@ -67,11 +67,51 @@
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power-monitor@40 {
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compatible = "ti,ina3221";
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_SYS_GPU";
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shunt-resistor-micro-ohms = <10000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_SYS_SOC";
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shunt-resistor-micro-ohms = <10000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_3V8_WIFI";
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shunt-resistor-micro-ohms = <10000>;
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};
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};
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power-monitor@41 {
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compatible = "ti,ina3221";
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reg = <0x41>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_IN";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_SYS_CPU";
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shunt-resistor-micro-ohms = <10000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_5V0_DDR";
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shunt-resistor-micro-ohms = <10000>;
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};
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};
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};
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@ -124,6 +164,17 @@
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i2c@c250000 {
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status = "okay";
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/* module ID EEPROM */
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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address-bits = <8>;
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page-size = <8>;
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size = <256>;
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read-only;
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};
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};
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rtc@c2a0000 {
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@ -70,6 +70,75 @@
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snps,rxpbl = <8>;
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};
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aconnect {
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compatible = "nvidia,tegra186-aconnect",
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"nvidia,tegra210-aconnect";
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clocks = <&bpmp TEGRA186_CLK_APE>,
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<&bpmp TEGRA186_CLK_APB2APE>;
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clock-names = "ape", "apb2ape";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x02900000 0x0 0x02900000 0x200000>;
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status = "disabled";
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dma-controller@2930000 {
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compatible = "nvidia,tegra186-adma";
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reg = <0x02930000 0x20000>;
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interrupt-parent = <&agic>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&bpmp TEGRA186_CLK_AHUB>;
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clock-names = "d_audio";
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status = "disabled";
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};
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agic: interrupt-controller@2a40000 {
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compatible = "nvidia,tegra186-agic",
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"nvidia,tegra210-agic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x02a41000 0x1000>,
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<0x02a42000 0x2000>;
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interrupts = <GIC_SPI 145
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&bpmp TEGRA186_CLK_APE>;
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clock-names = "clk";
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status = "disabled";
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};
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};
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memory-controller@2c00000 {
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compatible = "nvidia,tegra186-mc";
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reg = <0x0 0x02c00000 0x0 0xb0000>;
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@ -173,6 +242,9 @@
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C4>;
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reset-names = "i2c";
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pinctrl-names = "default", "idle";
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pinctrl-0 = <&state_dpaux1_i2c>;
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pinctrl-1 = <&state_dpaux1_off>;
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status = "disabled";
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};
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@ -201,6 +273,9 @@
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C6>;
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reset-names = "i2c";
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pinctrl-names = "default", "idle";
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pinctrl-0 = <&state_dpaux_i2c>;
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pinctrl-1 = <&state_dpaux_off>;
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status = "disabled";
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};
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@ -1121,47 +1196,6 @@
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "nvidia,tegra186-denver";
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device_type = "cpu";
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reg = <0x000>;
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};
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cpu@1 {
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compatible = "nvidia,tegra186-denver";
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device_type = "cpu";
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reg = <0x001>;
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};
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cpu@2 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu@3 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu@4 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu@5 {
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compatible = "arm,cortex-a57";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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iommus = <&smmu TEGRA186_SID_BPMP>;
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@ -1186,6 +1220,107 @@
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "nvidia,tegra186-denver";
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device_type = "cpu";
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i-cache-size = <0x20000>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
|
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next-level-cache = <&L2_DENVER>;
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reg = <0x000>;
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};
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|
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cpu@1 {
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compatible = "nvidia,tegra186-denver";
|
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device_type = "cpu";
|
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i-cache-size = <0x20000>;
|
||||
i-cache-line-size = <64>;
|
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i-cache-sets = <512>;
|
||||
d-cache-size = <0x10000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_DENVER>;
|
||||
reg = <0x001>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a57";
|
||||
device_type = "cpu";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_A57>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a57";
|
||||
device_type = "cpu";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_A57>;
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
cpu@4 {
|
||||
compatible = "arm,cortex-a57";
|
||||
device_type = "cpu";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_A57>;
|
||||
reg = <0x102>;
|
||||
};
|
||||
|
||||
cpu@5 {
|
||||
compatible = "arm,cortex-a57";
|
||||
device_type = "cpu";
|
||||
i-cache-size = <0xC000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_A57>;
|
||||
reg = <0x103>;
|
||||
};
|
||||
|
||||
L2_DENVER: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
};
|
||||
|
||||
L2_A57: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
a57 {
|
||||
polling-delay = <0>;
|
||||
|
|
@ -1294,5 +1429,6 @@
|
|||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#include <dt-bindings/mfd/max77620.h>
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Tegra194 P2888 Processor Module";
|
||||
model = "NVIDIA Jetson AGX Xavier";
|
||||
compatible = "nvidia,p2888", "nvidia,tegra194";
|
||||
|
||||
aliases {
|
||||
|
|
@ -191,7 +191,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sd3 {
|
||||
vdd_1v8ao: sd3 {
|
||||
regulator-name = "VDD_1V8AO";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
|
|
|||
|
|
@ -7,10 +7,22 @@
|
|||
#include "tegra194-p2888.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NVIDIA Jetson AGX Xavier Development Kit";
|
||||
model = "NVIDIA Jetson AGX Xavier Developer Kit";
|
||||
compatible = "nvidia,p2972-0000", "nvidia,tegra194";
|
||||
|
||||
cbb {
|
||||
aconnect {
|
||||
status = "okay";
|
||||
|
||||
dma-controller@2930000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
interrupt-controller@2a40000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
ddc: i2c@31c0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -52,6 +64,47 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie@14100000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
phys = <&p2u_hsio_0>;
|
||||
phy-names = "p2u-0";
|
||||
};
|
||||
|
||||
pcie@14140000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
phys = <&p2u_hsio_7>;
|
||||
phy-names = "p2u-0";
|
||||
};
|
||||
|
||||
pcie@14180000 {
|
||||
status = "okay";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
|
||||
<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
pcie@141a0000 {
|
||||
status = "disabled";
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
|
||||
fan: fan {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&pwm4 0 45334>;
|
||||
|
|
|
|||
|
|
@ -59,6 +59,77 @@
|
|||
snps,rxpbl = <8>;
|
||||
};
|
||||
|
||||
aconnect {
|
||||
compatible = "nvidia,tegra194-aconnect",
|
||||
"nvidia,tegra210-aconnect";
|
||||
clocks = <&bpmp TEGRA194_CLK_APE>,
|
||||
<&bpmp TEGRA194_CLK_APB2APE>;
|
||||
clock-names = "ape", "apb2ape";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x02900000 0x02900000 0x200000>;
|
||||
status = "disabled";
|
||||
|
||||
dma-controller@2930000 {
|
||||
compatible = "nvidia,tegra194-adma",
|
||||
"nvidia,tegra186-adma";
|
||||
reg = <0x02930000 0x20000>;
|
||||
interrupt-parent = <&agic>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&bpmp TEGRA194_CLK_AHUB>;
|
||||
clock-names = "d_audio";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
agic: interrupt-controller@2a40000 {
|
||||
compatible = "nvidia,tegra194-agic",
|
||||
"nvidia,tegra210-agic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x02a41000 0x1000>,
|
||||
<0x02a42000 0x2000>;
|
||||
interrupts = <GIC_SPI 145
|
||||
(GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&bpmp TEGRA194_CLK_APE>;
|
||||
clock-names = "clk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
uarta: serial@3100000 {
|
||||
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x03100000 0x40>;
|
||||
|
|
@ -423,6 +494,166 @@
|
|||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
p2u_hsio_0: phy@3e10000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e10000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_1: phy@3e20000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_2: phy@3e30000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_3: phy@3e40000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_4: phy@3e50000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e50000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_5: phy@3e60000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e60000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_6: phy@3e70000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e70000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_7: phy@3e80000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e80000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_8: phy@3e90000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03e90000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_9: phy@3ea0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03ea0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_0: phy@3eb0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03eb0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_1: phy@3ec0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03ec0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_2: phy@3ed0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03ed0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_3: phy@3ee0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03ee0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_4: phy@3ef0000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03ef0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_5: phy@3f00000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03f00000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_6: phy@3f10000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03f10000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_7: phy@3f20000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03f20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_10: phy@3f30000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03f30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_11: phy@3f40000 {
|
||||
compatible = "nvidia,tegra194-p2u";
|
||||
reg = <0x03f40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hsp_aon: hsp@c150000 {
|
||||
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
|
||||
reg = <0x0c150000 0xa0000>;
|
||||
|
|
@ -886,6 +1117,283 @@
|
|||
};
|
||||
};
|
||||
|
||||
pcie@14100000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_1>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 1>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
|
||||
0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
|
||||
};
|
||||
|
||||
pcie@14120000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_2>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 2>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
|
||||
0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
|
||||
};
|
||||
|
||||
pcie@14140000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
||||
reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <1>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <3>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_3>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 3>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
|
||||
0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
|
||||
};
|
||||
|
||||
pcie@14160000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
||||
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <4>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_4>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 4>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
|
||||
0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
|
||||
};
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
|
||||
0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
|
||||
};
|
||||
|
||||
pcie@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
|
||||
0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
num-viewport = <8>;
|
||||
linux,pci-domain = <5>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
|
||||
<&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
|
||||
clock-names = "core", "core_m";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
||||
0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
|
||||
0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
|
||||
};
|
||||
|
||||
sysram@40000000 {
|
||||
compatible = "nvidia,tegra194-sysram", "mmio-sram";
|
||||
reg = <0x0 0x40000000 0x0 0x50000>;
|
||||
|
|
@ -1053,5 +1561,6 @@
|
|||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
always-on;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -264,6 +264,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
/* module ID EEPROM */
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
|
||||
address-bits = <8>;
|
||||
page-size = <8>;
|
||||
size = <256>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
|
@ -328,7 +341,8 @@
|
|||
regulator-max-microvolt = <1320000>;
|
||||
enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
||||
regulator-ramp-delay = <80>;
|
||||
regulator-enable-ramp-delay = <1000>;
|
||||
regulator-enable-ramp-delay = <2000>;
|
||||
regulator-settling-time-us = <160>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,6 +79,19 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
/* carrier board ID EEPROM */
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
|
||||
address-bits = <8>;
|
||||
page-size = <8>;
|
||||
size = <256>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
clock@70110000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -88,6 +88,35 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
|
||||
address-bits = <8>;
|
||||
page-size = <8>;
|
||||
size = <256>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
|
||||
address-bits = <8>;
|
||||
page-size = <8>;
|
||||
size = <256>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_ddc: i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
|
@ -515,6 +544,12 @@
|
|||
cpu@3 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
idle-states {
|
||||
cpu-sleep {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
@ -633,17 +668,16 @@
|
|||
};
|
||||
|
||||
vdd_gpu: regulator@6 {
|
||||
compatible = "regulator-fixed";
|
||||
compatible = "pwm-regulator";
|
||||
reg = <6>;
|
||||
|
||||
pwms = <&pwm 1 4880>;
|
||||
regulator-name = "VDD_GPU";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-enable-ramp-delay = <250>;
|
||||
|
||||
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
|
||||
regulator-min-microvolt = <710000>;
|
||||
regulator-max-microvolt = <1320000>;
|
||||
regulator-ramp-delay = <80>;
|
||||
regulator-enable-ramp-delay = <2000>;
|
||||
regulator-settling-time-us = <160>;
|
||||
enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vdd_5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,6 +48,11 @@
|
|||
<&tegra_car 72>,
|
||||
<&tegra_car 74>;
|
||||
reset-names = "pex", "afi", "pcie_x";
|
||||
|
||||
pinctrl-names = "default", "idle";
|
||||
pinctrl-0 = <&pex_dpd_disable>;
|
||||
pinctrl-1 = <&pex_dpd_enable>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
|
|
@ -848,6 +853,20 @@
|
|||
pins = "sdmmc3";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
pex_dpd_disable: pex_en {
|
||||
pex-dpd-disable {
|
||||
pins = "pex-bias", "pex-clk1", "pex-clk2";
|
||||
low-power-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pex_dpd_enable: pex_dis {
|
||||
pex-dpd-enable {
|
||||
pins = "pex-bias", "pex-clk1", "pex-clk2";
|
||||
low-power-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fuse@7000f800 {
|
||||
|
|
@ -1258,7 +1277,7 @@
|
|||
compatible = "nvidia,tegra210-agic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x702f9000 0x2000>,
|
||||
reg = <0x702f9000 0x1000>,
|
||||
<0x702fa000 0x2000>;
|
||||
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>;
|
||||
|
|
@ -1430,6 +1449,7 @@
|
|||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soctherm: thermal-sensor@700e2000 {
|
||||
|
|
|
|||
|
|
@ -41,34 +41,6 @@
|
|||
#define TEGRA186_MAIN_GPIO(port, offset) \
|
||||
((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
/* need to keep these for backwards-compatibility */
|
||||
#define TEGRA_MAIN_GPIO_PORT_A 0
|
||||
#define TEGRA_MAIN_GPIO_PORT_B 1
|
||||
#define TEGRA_MAIN_GPIO_PORT_C 2
|
||||
#define TEGRA_MAIN_GPIO_PORT_D 3
|
||||
#define TEGRA_MAIN_GPIO_PORT_E 4
|
||||
#define TEGRA_MAIN_GPIO_PORT_F 5
|
||||
#define TEGRA_MAIN_GPIO_PORT_G 6
|
||||
#define TEGRA_MAIN_GPIO_PORT_H 7
|
||||
#define TEGRA_MAIN_GPIO_PORT_I 8
|
||||
#define TEGRA_MAIN_GPIO_PORT_J 9
|
||||
#define TEGRA_MAIN_GPIO_PORT_K 10
|
||||
#define TEGRA_MAIN_GPIO_PORT_L 11
|
||||
#define TEGRA_MAIN_GPIO_PORT_M 12
|
||||
#define TEGRA_MAIN_GPIO_PORT_N 13
|
||||
#define TEGRA_MAIN_GPIO_PORT_O 14
|
||||
#define TEGRA_MAIN_GPIO_PORT_P 15
|
||||
#define TEGRA_MAIN_GPIO_PORT_Q 16
|
||||
#define TEGRA_MAIN_GPIO_PORT_R 17
|
||||
#define TEGRA_MAIN_GPIO_PORT_T 18
|
||||
#define TEGRA_MAIN_GPIO_PORT_X 19
|
||||
#define TEGRA_MAIN_GPIO_PORT_Y 20
|
||||
#define TEGRA_MAIN_GPIO_PORT_BB 21
|
||||
#define TEGRA_MAIN_GPIO_PORT_CC 22
|
||||
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||||
#define TEGRA_MAIN_GPIO(port, offset) \
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||||
((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
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||||
|
||||
/* GPIOs implemented by AON GPIO controller */
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||||
#define TEGRA186_AON_GPIO_PORT_S 0
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||||
#define TEGRA186_AON_GPIO_PORT_U 1
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||||
|
|
@ -82,17 +54,4 @@
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|||
#define TEGRA186_AON_GPIO(port, offset) \
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||||
((TEGRA186_AON_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
/* need to keep these for backwards-compatibility */
|
||||
#define TEGRA_AON_GPIO_PORT_S 0
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||||
#define TEGRA_AON_GPIO_PORT_U 1
|
||||
#define TEGRA_AON_GPIO_PORT_V 2
|
||||
#define TEGRA_AON_GPIO_PORT_W 3
|
||||
#define TEGRA_AON_GPIO_PORT_Z 4
|
||||
#define TEGRA_AON_GPIO_PORT_AA 5
|
||||
#define TEGRA_AON_GPIO_PORT_EE 6
|
||||
#define TEGRA_AON_GPIO_PORT_FF 7
|
||||
|
||||
#define TEGRA_AON_GPIO(port, offset) \
|
||||
((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue