sfc: Add EF10 register and structure definitions
Also update comments and assertions in io.h: - EF10 does not have a general BIU collector and does not have the bug affecting TIMER_COMMAND_REG[0] on Falcon/Siena - The WPTR field moved within RX_DESC_UPD_REG and TX_DESC_UPD_REG. Adjust efx_writed_page() accordingly Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
This commit is contained in:
Ben Hutchings
parent
ba8977bdb2
commit
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2012-2013 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_EF10_REGS_H
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#define EFX_EF10_REGS_H
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/* EF10 hardware architecture definitions have a name prefix following
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* the format:
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*
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* E<type>_<min-rev><max-rev>_
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*
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* The following <type> strings are used:
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*
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* MMIO register Host memory structure
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* -------------------------------------------------------------
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* Address R
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* Bitfield RF SF
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* Enumerator FE SE
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*
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* <min-rev> is the first revision to which the definition applies:
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*
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* D: Huntington A0
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*
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* If the definition has been changed or removed in later revisions
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* then <max-rev> is the last revision to which the definition applies;
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* otherwise it is "Z".
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*/
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/**************************************************************************
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*
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* EF10 registers and descriptors
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*
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**************************************************************************
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*/
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/* BIU_HW_REV_ID_REG: */
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#define ER_DZ_BIU_HW_REV_ID 0x00000000
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#define ERF_DZ_HW_REV_ID_LBN 0
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#define ERF_DZ_HW_REV_ID_WIDTH 32
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/* BIU_MC_SFT_STATUS_REG: */
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#define ER_DZ_BIU_MC_SFT_STATUS 0x00000010
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#define ER_DZ_BIU_MC_SFT_STATUS_STEP 4
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#define ER_DZ_BIU_MC_SFT_STATUS_ROWS 8
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#define ERF_DZ_MC_SFT_STATUS_LBN 0
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#define ERF_DZ_MC_SFT_STATUS_WIDTH 32
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/* BIU_INT_ISR_REG: */
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#define ER_DZ_BIU_INT_ISR 0x00000090
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#define ERF_DZ_ISR_REG_LBN 0
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#define ERF_DZ_ISR_REG_WIDTH 32
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/* MC_DB_LWRD_REG: */
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#define ER_DZ_MC_DB_LWRD 0x00000200
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#define ERF_DZ_MC_DOORBELL_L_LBN 0
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#define ERF_DZ_MC_DOORBELL_L_WIDTH 32
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/* MC_DB_HWRD_REG: */
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#define ER_DZ_MC_DB_HWRD 0x00000204
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#define ERF_DZ_MC_DOORBELL_H_LBN 0
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#define ERF_DZ_MC_DOORBELL_H_WIDTH 32
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/* EVQ_RPTR_REG: */
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#define ER_DZ_EVQ_RPTR 0x00000400
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#define ER_DZ_EVQ_RPTR_STEP 8192
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#define ER_DZ_EVQ_RPTR_ROWS 2048
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#define ERF_DZ_EVQ_RPTR_VLD_LBN 15
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#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
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#define ERF_DZ_EVQ_RPTR_LBN 0
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#define ERF_DZ_EVQ_RPTR_WIDTH 15
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/* EVQ_TMR_REG: */
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#define ER_DZ_EVQ_TMR 0x00000420
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#define ER_DZ_EVQ_TMR_STEP 8192
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#define ER_DZ_EVQ_TMR_ROWS 2048
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#define ERF_DZ_TC_TIMER_MODE_LBN 14
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#define ERF_DZ_TC_TIMER_MODE_WIDTH 2
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#define ERF_DZ_TC_TIMER_VAL_LBN 0
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#define ERF_DZ_TC_TIMER_VAL_WIDTH 14
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/* RX_DESC_UPD_REG: */
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#define ER_DZ_RX_DESC_UPD 0x00000830
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#define ER_DZ_RX_DESC_UPD_STEP 8192
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#define ER_DZ_RX_DESC_UPD_ROWS 2048
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#define ERF_DZ_RX_DESC_WPTR_LBN 0
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#define ERF_DZ_RX_DESC_WPTR_WIDTH 12
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/* TX_DESC_UPD_REG: */
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#define ER_DZ_TX_DESC_UPD 0x00000a10
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#define ER_DZ_TX_DESC_UPD_STEP 8192
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#define ER_DZ_TX_DESC_UPD_ROWS 2048
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#define ERF_DZ_RSVD_LBN 76
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#define ERF_DZ_RSVD_WIDTH 20
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#define ERF_DZ_TX_DESC_WPTR_LBN 64
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#define ERF_DZ_TX_DESC_WPTR_WIDTH 12
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#define ERF_DZ_TX_DESC_HWORD_LBN 32
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#define ERF_DZ_TX_DESC_HWORD_WIDTH 32
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#define ERF_DZ_TX_DESC_LWORD_LBN 0
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#define ERF_DZ_TX_DESC_LWORD_WIDTH 32
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/* DRIVER_EV */
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#define ESF_DZ_DRV_CODE_LBN 60
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#define ESF_DZ_DRV_CODE_WIDTH 4
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#define ESF_DZ_DRV_SUB_CODE_LBN 56
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#define ESF_DZ_DRV_SUB_CODE_WIDTH 4
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#define ESE_DZ_DRV_TIMER_EV 3
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#define ESE_DZ_DRV_START_UP_EV 2
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#define ESE_DZ_DRV_WAKE_UP_EV 1
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#define ESF_DZ_DRV_SUB_DATA_LBN 0
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#define ESF_DZ_DRV_SUB_DATA_WIDTH 56
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#define ESF_DZ_DRV_EVQ_ID_LBN 0
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#define ESF_DZ_DRV_EVQ_ID_WIDTH 14
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#define ESF_DZ_DRV_TMR_ID_LBN 0
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#define ESF_DZ_DRV_TMR_ID_WIDTH 14
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/* EVENT_ENTRY */
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#define ESF_DZ_EV_CODE_LBN 60
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#define ESF_DZ_EV_CODE_WIDTH 4
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#define ESE_DZ_EV_CODE_MCDI_EV 12
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#define ESE_DZ_EV_CODE_DRIVER_EV 5
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#define ESE_DZ_EV_CODE_TX_EV 2
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#define ESE_DZ_EV_CODE_RX_EV 0
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#define ESE_DZ_OTHER other
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#define ESF_DZ_EV_DATA_LBN 0
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#define ESF_DZ_EV_DATA_WIDTH 60
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/* MC_EVENT */
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#define ESF_DZ_MC_CODE_LBN 60
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#define ESF_DZ_MC_CODE_WIDTH 4
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#define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
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#define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
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#define ESF_DZ_MC_DROP_EVENT_LBN 58
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#define ESF_DZ_MC_DROP_EVENT_WIDTH 1
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#define ESF_DZ_MC_SOFT_LBN 0
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#define ESF_DZ_MC_SOFT_WIDTH 58
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/* RX_EVENT */
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#define ESF_DZ_RX_CODE_LBN 60
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#define ESF_DZ_RX_CODE_WIDTH 4
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#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
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#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
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#define ESF_DZ_RX_DROP_EVENT_LBN 58
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#define ESF_DZ_RX_DROP_EVENT_WIDTH 1
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#define ESF_DZ_RX_EV_RSVD2_LBN 54
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#define ESF_DZ_RX_EV_RSVD2_WIDTH 4
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#define ESF_DZ_RX_EV_SOFT2_LBN 52
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#define ESF_DZ_RX_EV_SOFT2_WIDTH 2
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#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
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#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
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#define ESF_DZ_RX_L4_CLASS_LBN 45
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#define ESF_DZ_RX_L4_CLASS_WIDTH 3
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#define ESE_DZ_L4_CLASS_RSVD7 7
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#define ESE_DZ_L4_CLASS_RSVD6 6
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#define ESE_DZ_L4_CLASS_RSVD5 5
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#define ESE_DZ_L4_CLASS_RSVD4 4
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#define ESE_DZ_L4_CLASS_RSVD3 3
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#define ESE_DZ_L4_CLASS_UDP 2
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#define ESE_DZ_L4_CLASS_TCP 1
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#define ESE_DZ_L4_CLASS_UNKNOWN 0
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#define ESF_DZ_RX_L3_CLASS_LBN 42
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#define ESF_DZ_RX_L3_CLASS_WIDTH 3
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#define ESE_DZ_L3_CLASS_RSVD7 7
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#define ESE_DZ_L3_CLASS_IP6_FRAG 6
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#define ESE_DZ_L3_CLASS_ARP 5
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#define ESE_DZ_L3_CLASS_IP4_FRAG 4
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#define ESE_DZ_L3_CLASS_FCOE 3
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#define ESE_DZ_L3_CLASS_IP6 2
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#define ESE_DZ_L3_CLASS_IP4 1
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#define ESE_DZ_L3_CLASS_UNKNOWN 0
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#define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
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#define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
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#define ESE_DZ_ETH_TAG_CLASS_RSVD7 7
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#define ESE_DZ_ETH_TAG_CLASS_RSVD6 6
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#define ESE_DZ_ETH_TAG_CLASS_RSVD5 5
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#define ESE_DZ_ETH_TAG_CLASS_RSVD4 4
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#define ESE_DZ_ETH_TAG_CLASS_RSVD3 3
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#define ESE_DZ_ETH_TAG_CLASS_VLAN2 2
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#define ESE_DZ_ETH_TAG_CLASS_VLAN1 1
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#define ESE_DZ_ETH_TAG_CLASS_NONE 0
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#define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
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#define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
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#define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
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#define ESE_DZ_ETH_BASE_CLASS_LLC 1
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#define ESE_DZ_ETH_BASE_CLASS_ETH2 0
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#define ESF_DZ_RX_MAC_CLASS_LBN 35
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#define ESF_DZ_RX_MAC_CLASS_WIDTH 1
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#define ESE_DZ_MAC_CLASS_MCAST 1
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#define ESE_DZ_MAC_CLASS_UCAST 0
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#define ESF_DZ_RX_EV_SOFT1_LBN 32
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#define ESF_DZ_RX_EV_SOFT1_WIDTH 3
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#define ESF_DZ_RX_EV_RSVD1_LBN 31
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#define ESF_DZ_RX_EV_RSVD1_WIDTH 1
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#define ESF_DZ_RX_ABORT_LBN 30
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#define ESF_DZ_RX_ABORT_WIDTH 1
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#define ESF_DZ_RX_ECC_ERR_LBN 29
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#define ESF_DZ_RX_ECC_ERR_WIDTH 1
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#define ESF_DZ_RX_CRC1_ERR_LBN 28
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#define ESF_DZ_RX_CRC1_ERR_WIDTH 1
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#define ESF_DZ_RX_CRC0_ERR_LBN 27
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#define ESF_DZ_RX_CRC0_ERR_WIDTH 1
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#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
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#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
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#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25
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#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
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#define ESF_DZ_RX_ECRC_ERR_LBN 24
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#define ESF_DZ_RX_ECRC_ERR_WIDTH 1
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#define ESF_DZ_RX_QLABEL_LBN 16
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#define ESF_DZ_RX_QLABEL_WIDTH 5
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#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
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#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
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#define ESF_DZ_RX_CONT_LBN 14
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#define ESF_DZ_RX_CONT_WIDTH 1
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#define ESF_DZ_RX_BYTES_LBN 0
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#define ESF_DZ_RX_BYTES_WIDTH 14
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/* RX_KER_DESC */
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#define ESF_DZ_RX_KER_RESERVED_LBN 62
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#define ESF_DZ_RX_KER_RESERVED_WIDTH 2
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#define ESF_DZ_RX_KER_BYTE_CNT_LBN 48
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#define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
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#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
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#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
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/* RX_USER_DESC */
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#define ESF_DZ_RX_USR_RESERVED_LBN 62
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#define ESF_DZ_RX_USR_RESERVED_WIDTH 2
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#define ESF_DZ_RX_USR_BYTE_CNT_LBN 48
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#define ESF_DZ_RX_USR_BYTE_CNT_WIDTH 14
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#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_LBN 44
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#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_WIDTH 4
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#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10
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#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8
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#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4
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#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0
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#define ESF_DZ_RX_USR_BUF_ID_OFFSET_LBN 0
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#define ESF_DZ_RX_USR_BUF_ID_OFFSET_WIDTH 44
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#define ESF_DZ_RX_USR_4KBPS_BUF_ID_LBN 12
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#define ESF_DZ_RX_USR_4KBPS_BUF_ID_WIDTH 32
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#define ESF_DZ_RX_USR_64KBPS_BUF_ID_LBN 16
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#define ESF_DZ_RX_USR_64KBPS_BUF_ID_WIDTH 28
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#define ESF_DZ_RX_USR_1MBPS_BUF_ID_LBN 20
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#define ESF_DZ_RX_USR_1MBPS_BUF_ID_WIDTH 24
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#define ESF_DZ_RX_USR_4MBPS_BUF_ID_LBN 22
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#define ESF_DZ_RX_USR_4MBPS_BUF_ID_WIDTH 22
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#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_LBN 0
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#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_WIDTH 22
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#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_LBN 0
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#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_WIDTH 20
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#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_LBN 0
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#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_WIDTH 16
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#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_LBN 0
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#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_WIDTH 12
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/* TX_CSUM_TSTAMP_DESC */
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#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
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#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
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#define ESF_DZ_TX_OPTION_TYPE_LBN 60
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#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
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#define ESE_DZ_TX_OPTION_DESC_TSO 7
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#define ESE_DZ_TX_OPTION_DESC_VLAN 6
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#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
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#define ESF_DZ_TX_TIMESTAMP_LBN 5
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#define ESF_DZ_TX_TIMESTAMP_WIDTH 1
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#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
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#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
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#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
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#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
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#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
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#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
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#define ESE_DZ_TX_OPTION_CRC_FCOE 1
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#define ESE_DZ_TX_OPTION_CRC_OFF 0
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#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
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#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
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#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
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#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
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/* TX_EVENT */
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#define ESF_DZ_TX_CODE_LBN 60
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#define ESF_DZ_TX_CODE_WIDTH 4
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#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
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#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
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#define ESF_DZ_TX_DROP_EVENT_LBN 58
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#define ESF_DZ_TX_DROP_EVENT_WIDTH 1
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#define ESF_DZ_TX_EV_RSVD_LBN 48
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#define ESF_DZ_TX_EV_RSVD_WIDTH 10
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#define ESF_DZ_TX_SOFT2_LBN 32
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#define ESF_DZ_TX_SOFT2_WIDTH 16
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#define ESF_DZ_TX_CAN_MERGE_LBN 31
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#define ESF_DZ_TX_CAN_MERGE_WIDTH 1
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#define ESF_DZ_TX_SOFT1_LBN 24
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#define ESF_DZ_TX_SOFT1_WIDTH 7
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#define ESF_DZ_TX_QLABEL_LBN 16
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#define ESF_DZ_TX_QLABEL_WIDTH 5
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#define ESF_DZ_TX_DESCR_INDX_LBN 0
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#define ESF_DZ_TX_DESCR_INDX_WIDTH 16
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/* TX_KER_DESC */
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#define ESF_DZ_TX_KER_TYPE_LBN 63
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#define ESF_DZ_TX_KER_TYPE_WIDTH 1
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#define ESF_DZ_TX_KER_CONT_LBN 62
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#define ESF_DZ_TX_KER_CONT_WIDTH 1
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#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48
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#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
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#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
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#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
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/* TX_PIO_DESC */
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#define ESF_DZ_TX_PIO_TYPE_LBN 63
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#define ESF_DZ_TX_PIO_TYPE_WIDTH 1
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#define ESF_DZ_TX_PIO_OPT_LBN 60
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#define ESF_DZ_TX_PIO_OPT_WIDTH 3
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#define ESF_DZ_TX_PIO_CONT_LBN 59
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#define ESF_DZ_TX_PIO_CONT_WIDTH 1
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#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
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#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
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#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
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#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
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/* TX_TSO_DESC */
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#define ESF_DZ_TX_DESC_IS_OPT_LBN 63
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#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
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#define ESF_DZ_TX_OPTION_TYPE_LBN 60
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#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3
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#define ESE_DZ_TX_OPTION_DESC_TSO 7
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#define ESE_DZ_TX_OPTION_DESC_VLAN 6
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#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
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#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
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#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
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#define ESF_DZ_TX_TSO_IP_ID_LBN 32
|
||||
#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16
|
||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
|
||||
#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
|
||||
|
||||
/* TX_USER_DESC */
|
||||
#define ESF_DZ_TX_USR_TYPE_LBN 63
|
||||
#define ESF_DZ_TX_USR_TYPE_WIDTH 1
|
||||
#define ESF_DZ_TX_USR_CONT_LBN 62
|
||||
#define ESF_DZ_TX_USR_CONT_WIDTH 1
|
||||
#define ESF_DZ_TX_USR_BYTE_CNT_LBN 48
|
||||
#define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14
|
||||
#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44
|
||||
#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_WIDTH 4
|
||||
#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10
|
||||
#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8
|
||||
#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4
|
||||
#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0
|
||||
#define ESF_DZ_TX_USR_BUF_ID_OFFSET_LBN 0
|
||||
#define ESF_DZ_TX_USR_BUF_ID_OFFSET_WIDTH 44
|
||||
#define ESF_DZ_TX_USR_4KBPS_BUF_ID_LBN 12
|
||||
#define ESF_DZ_TX_USR_4KBPS_BUF_ID_WIDTH 32
|
||||
#define ESF_DZ_TX_USR_64KBPS_BUF_ID_LBN 16
|
||||
#define ESF_DZ_TX_USR_64KBPS_BUF_ID_WIDTH 28
|
||||
#define ESF_DZ_TX_USR_1MBPS_BUF_ID_LBN 20
|
||||
#define ESF_DZ_TX_USR_1MBPS_BUF_ID_WIDTH 24
|
||||
#define ESF_DZ_TX_USR_4MBPS_BUF_ID_LBN 22
|
||||
#define ESF_DZ_TX_USR_4MBPS_BUF_ID_WIDTH 22
|
||||
#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_LBN 0
|
||||
#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_WIDTH 22
|
||||
#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_LBN 0
|
||||
#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_WIDTH 20
|
||||
#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_LBN 0
|
||||
#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_WIDTH 16
|
||||
#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_LBN 0
|
||||
#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_WIDTH 12
|
||||
/*************************************************************************/
|
||||
|
||||
/* TX_DESC_UPD_REG: Transmit descriptor update register.
|
||||
* We may write just one dword of these registers.
|
||||
*/
|
||||
#define ER_DZ_TX_DESC_UPD_DWORD (ER_DZ_TX_DESC_UPD + 2 * 4)
|
||||
#define ERF_DZ_TX_DESC_WPTR_DWORD_LBN (ERF_DZ_TX_DESC_WPTR_LBN - 2 * 32)
|
||||
#define ERF_DZ_TX_DESC_WPTR_DWORD_WIDTH ERF_DZ_TX_DESC_WPTR_WIDTH
|
||||
|
||||
/* The workaround for bug 35388 requires multiplexing writes through
|
||||
* the TX_DESC_UPD_DWORD address.
|
||||
* TX_DESC_UPD: 0ppppppppppp (bit 11 lost)
|
||||
* EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits)
|
||||
* EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost)
|
||||
*/
|
||||
#define ER_DD_EVQ_INDIRECT ER_DZ_TX_DESC_UPD_DWORD
|
||||
#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
|
||||
#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
|
||||
#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
|
||||
#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
|
||||
#define ERF_DD_EVQ_IND_RPTR_LBN 0
|
||||
#define ERF_DD_EVQ_IND_RPTR_WIDTH 8
|
||||
#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
|
||||
#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
|
||||
#define EFE_DD_EVQ_IND_TIMER_FLAGS 3
|
||||
#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
|
||||
#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
|
||||
#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
|
||||
#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
|
||||
|
||||
/* TX_PIOBUF
|
||||
* PIO buffer aperture (paged)
|
||||
*/
|
||||
#define ER_DZ_TX_PIOBUF 4096
|
||||
#define ER_DZ_TX_PIOBUF_SIZE 2048
|
||||
|
||||
/* RX packet prefix */
|
||||
#define ES_DZ_RX_PREFIX_HASH_OFST 0
|
||||
#define ES_DZ_RX_PREFIX_VLAN1_OFST 4
|
||||
#define ES_DZ_RX_PREFIX_VLAN2_OFST 6
|
||||
#define ES_DZ_RX_PREFIX_PKTLEN_OFST 8
|
||||
#define ES_DZ_RX_PREFIX_TSTAMP_OFST 10
|
||||
#define ES_DZ_RX_PREFIX_SIZE 14
|
||||
|
||||
#endif /* EFX_EF10_REGS_H */
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
*
|
||||
**************************************************************************
|
||||
*
|
||||
* Notes on locking strategy:
|
||||
* Notes on locking strategy for the Falcon architecture:
|
||||
*
|
||||
* Many CSRs are very wide and cannot be read or written atomically.
|
||||
* Writes from the host are buffered by the Bus Interface Unit (BIU)
|
||||
|
|
@ -54,6 +54,12 @@
|
|||
* register while the collector already holds values for some other
|
||||
* register, the write is discarded and the collector maintains its
|
||||
* current state.
|
||||
*
|
||||
* The EF10 architecture exposes very few registers to the host and
|
||||
* most of them are only 32 bits wide. The only exceptions are the MC
|
||||
* doorbell register pair, which has its own latching, and
|
||||
* TX_DESC_UPD, which works in a similar way to the Falcon
|
||||
* architecture.
|
||||
*/
|
||||
|
||||
#if BITS_PER_LONG == 64
|
||||
|
|
@ -237,8 +243,8 @@ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
|
|||
BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
|
||||
page)
|
||||
|
||||
/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
|
||||
* RX_DESC_UPD or TX_DESC_UPD)
|
||||
/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
|
||||
* high bits of RX_DESC_UPD or TX_DESC_UPD)
|
||||
*/
|
||||
static inline void
|
||||
_efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
|
||||
|
|
@ -249,8 +255,12 @@ _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value,
|
|||
#define efx_writed_page(efx, value, reg, page) \
|
||||
_efx_writed_page(efx, value, \
|
||||
reg + \
|
||||
BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
|
||||
&& (reg) != 0xa1c), \
|
||||
BUILD_BUG_ON_ZERO((reg) != 0x400 && \
|
||||
(reg) != 0x420 && \
|
||||
(reg) != 0x830 && \
|
||||
(reg) != 0x83c && \
|
||||
(reg) != 0xa18 && \
|
||||
(reg) != 0xa1c), \
|
||||
page)
|
||||
|
||||
/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
|
||||
|
|
|
|||
Loading…
Reference in New Issue