tty: serial: fsl_lpuart: Flush HW FIFOs in .flush_buffer
Switching baud rate might cause bogus data to appear in HW FIFO. Add code to do a HW FIFO flush to .flush_buffer callback to avoid that. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-imx@nxp.com Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20190729195226.8862-4-andrew.smirnov@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -518,9 +518,16 @@ static int lpuart_dma_tx_request(struct uart_port *port)
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return 0;
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}
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static bool lpuart_is_32(struct lpuart_port *sport)
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{
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return sport->port.iotype == UPIO_MEM32 ||
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sport->port.iotype == UPIO_MEM32BE;
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}
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static void lpuart_flush_buffer(struct uart_port *port)
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{
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struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
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u32 val;
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if (sport->lpuart_dma_tx_use) {
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if (sport->dma_tx_in_progress) {
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@ -530,6 +537,16 @@ static void lpuart_flush_buffer(struct uart_port *port)
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}
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dmaengine_terminate_all(sport->dma_tx_chan);
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}
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if (lpuart_is_32(sport)) {
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val = lpuart32_read(&sport->port, UARTFIFO);
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val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
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lpuart32_write(&sport->port, val, UARTFIFO);
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} else {
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val = readb(sport->port.membase + UARTPFIFO);
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val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
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writeb(val, sport->port.membase + UARTCFIFO);
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}
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}
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#if defined(CONFIG_CONSOLE_POLL)
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@ -754,12 +771,6 @@ static unsigned int lpuart32_tx_empty(struct uart_port *port)
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return 0;
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}
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static bool lpuart_is_32(struct lpuart_port *sport)
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{
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return sport->port.iotype == UPIO_MEM32 ||
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sport->port.iotype == UPIO_MEM32BE;
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}
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static irqreturn_t lpuart_txint(int irq, void *dev_id)
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{
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struct lpuart_port *sport = dev_id;
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