drm/amd/display: Add green_sardine support to DC

Display Core support for green_sardine

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li 2020-10-08 13:28:41 -04:00 committed by Alex Deucher
parent 7cc656e2d0
commit 9ba93114c4
4 changed files with 25 additions and 0 deletions

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@ -17,6 +17,14 @@ config DRM_AMD_DC_DCN
help help
Raven, Navi and Renoir family support for display engine Raven, Navi and Renoir family support for display engine
config DRM_AMD_DC_GREEN_SARDINE
bool "Green Sardine support"
default y
depends on DRM_AMD_DC_DCN
help
Choose this option if you want to have
Green Sardine support for display engine
config DRM_AMD_DC_DCN3_0 config DRM_AMD_DC_DCN3_0
bool "DCN 3.0 family" bool "DCN 3.0 family"
depends on DRM_AMD_DC && X86 depends on DRM_AMD_DC && X86

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@ -169,6 +169,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break; break;
} }
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break;
}
#endif
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) { if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
break; break;

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@ -126,6 +126,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
dc_version = DCN_VERSION_1_01; dc_version = DCN_VERSION_1_01;
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1; dc_version = DCN_VERSION_2_1;
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
#endif
break; break;
#endif #endif

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@ -209,6 +209,12 @@ enum {
#if defined(CONFIG_DRM_AMD_DC_DCN3_02) #if defined(CONFIG_DRM_AMD_DC_DCN3_02)
#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
#endif #endif
#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
#define GREEN_SARDINE_A0 0xA1
#ifndef ASICREV_IS_GREEN_SARDINE
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
#endif
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_01) #if defined(CONFIG_DRM_AMD_DC_DCN3_01)
#define FAMILY_VGH 144 #define FAMILY_VGH 144
#define DEVICE_ID_VGH_163F 0x163F #define DEVICE_ID_VGH_163F 0x163F