drm/amd/display: Add green_sardine support to DC
Display Core support for green_sardine Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -17,6 +17,14 @@ config DRM_AMD_DC_DCN
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help
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help
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Raven, Navi and Renoir family support for display engine
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Raven, Navi and Renoir family support for display engine
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config DRM_AMD_DC_GREEN_SARDINE
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bool "Green Sardine support"
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default y
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depends on DRM_AMD_DC_DCN
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help
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Choose this option if you want to have
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Green Sardine support for display engine
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config DRM_AMD_DC_DCN3_0
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config DRM_AMD_DC_DCN3_0
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bool "DCN 3.0 family"
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bool "DCN 3.0 family"
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depends on DRM_AMD_DC && X86
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depends on DRM_AMD_DC && X86
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@ -169,6 +169,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
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rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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break;
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break;
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
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if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
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rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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break;
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}
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#endif
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if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
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if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
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rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
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rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
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break;
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break;
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@ -126,6 +126,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
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dc_version = DCN_VERSION_1_01;
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dc_version = DCN_VERSION_1_01;
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if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
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if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
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dc_version = DCN_VERSION_2_1;
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dc_version = DCN_VERSION_2_1;
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#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
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if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
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dc_version = DCN_VERSION_2_1;
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#endif
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break;
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break;
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#endif
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#endif
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@ -209,6 +209,12 @@ enum {
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#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_02)
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#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
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#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
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#endif
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#endif
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#if defined(CONFIG_DRM_AMD_DC_GREEN_SARDINE)
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#define GREEN_SARDINE_A0 0xA1
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#ifndef ASICREV_IS_GREEN_SARDINE
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#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
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#endif
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
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#define FAMILY_VGH 144
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#define FAMILY_VGH 144
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#define DEVICE_ID_VGH_163F 0x163F
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#define DEVICE_ID_VGH_163F 0x163F
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