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ARM: dts: exynos: use hyphens in Exynos5 node names 

Use hyphens instead of underscores in the Exynos5250 and Exynos542x node
names which is expected by naming convention, multiple dtschema files
and pointed out by dtc W=2 builds.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201105184506.215648-4-krzk@kernel.org
This commit is contained in:
Krzysztof Kozlowski 2020-11-05 19:45:04 +01:00
parent 32f9abc326
commit 9b846ba7c1
3 changed files with 35 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -70,7 +70,7 @@
};
};
cpu0_opp_table: opp_table0 {
cpu0_opp_table: opp-table0 {
compatible = "operating-points-v2";
opp-shared;

36
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -42,7 +42,7 @@
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
*/
cluster_a15_opp_table: opp_table0 {
cluster_a15_opp_table: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
@ -108,7 +108,7 @@
};
};
cluster_a7_opp_table: opp_table1 {
cluster_a7_opp_table: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
@ -1077,112 +1077,112 @@
#iommu-cells = <0>;
};
bus_wcore: bus_wcore {
bus_wcore: bus-wcore {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
status = "disabled";
};
bus_noc: bus_noc {
bus_noc: bus-noc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
status = "disabled";
};
bus_fsys_apb: bus_fsys_apb {
bus_fsys_apb: bus-fsys-apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
status = "disabled";
};
bus_fsys: bus_fsys {
bus_fsys: bus-fsys {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
status = "disabled";
};
bus_fsys2: bus_fsys2 {
bus_fsys2: bus-fsys2 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
status = "disabled";
};
bus_mfc: bus_mfc {
bus_mfc: bus-mfc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
status = "disabled";
};
bus_gen: bus_gen {
bus_gen: bus-gen {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
status = "disabled";
};
bus_peri: bus_peri {
bus_peri: bus-peri {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
status = "disabled";
};
bus_g2d: bus_g2d {
bus_g2d: bus-g2d {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
status = "disabled";
};
bus_g2d_acp: bus_g2d_acp {
bus_g2d_acp: bus-g2d-acp {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
status = "disabled";
};
bus_jpeg: bus_jpeg {
bus_jpeg: bus-jpeg {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
status = "disabled";
};
bus_jpeg_apb: bus_jpeg_apb {
bus_jpeg_apb: bus-jpeg-apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
status = "disabled";
};
bus_disp1_fimd: bus_disp1_fimd {
bus_disp1_fimd: bus-disp1-fimd {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
status = "disabled";
};
bus_disp1: bus_disp1 {
bus_disp1: bus-disp1 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
status = "disabled";
};
bus_gscl_scaler: bus_gscl_scaler {
bus_gscl_scaler: bus-gscl-scaler {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
status = "disabled";
};
bus_mscl: bus_mscl {
bus_mscl: bus-mscl {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";

32
arch/arm/boot/dts/exynos5422-odroid-core.dtsi
View File

@ -35,7 +35,7 @@
};
};
bus_wcore_opp_table: opp_table2 {
bus_wcore_opp_table: opp-table2 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@ -61,7 +61,7 @@
};
};
bus_noc_opp_table: opp_table3 {
bus_noc_opp_table: opp-table3 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -79,7 +79,7 @@
};
};
bus_fsys_apb_opp_table: opp_table4 {
bus_fsys_apb_opp_table: opp-table4 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -91,7 +91,7 @@
};
};
bus_fsys2_opp_table: opp_table5 {
bus_fsys2_opp_table: opp-table5 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@ -106,7 +106,7 @@
};
};
bus_mfc_opp_table: opp_table6 {
bus_mfc_opp_table: opp-table6 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -127,7 +127,7 @@
};
};
bus_gen_opp_table: opp_table7 {
bus_gen_opp_table: opp-table7 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@ -145,7 +145,7 @@
};
};
bus_peri_opp_table: opp_table8 {
bus_peri_opp_table: opp-table8 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -154,7 +154,7 @@
};
};
bus_g2d_opp_table: opp_table9 {
bus_g2d_opp_table: opp-table9 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -175,7 +175,7 @@
};
};
bus_g2d_acp_opp_table: opp_table10 {
bus_g2d_acp_opp_table: opp-table10 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
@ -193,7 +193,7 @@
};
};
bus_jpeg_opp_table: opp_table11 {
bus_jpeg_opp_table: opp-table11 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@ -211,7 +211,7 @@
};
};
bus_jpeg_apb_opp_table: opp_table12 {
bus_jpeg_apb_opp_table: opp-table12 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -229,7 +229,7 @@
};
};
bus_disp1_fimd_opp_table: opp_table13 {
bus_disp1_fimd_opp_table: opp-table13 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@ -241,7 +241,7 @@
};
};
bus_disp1_opp_table: opp_table14 {
bus_disp1_opp_table: opp-table14 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@ -256,7 +256,7 @@
};
};
bus_gscl_opp_table: opp_table15 {
bus_gscl_opp_table: opp-table15 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
@ -271,7 +271,7 @@
};
};
bus_mscl_opp_table: opp_table16 {
bus_mscl_opp_table: opp-table16 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
@ -292,7 +292,7 @@
};
};
dmc_opp_table: opp_table17 {
dmc_opp_table: opp-table17 {
compatible = "operating-points-v2";
opp00 {