UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core 

Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Fabrizio Castro 2018-12-14 09:10:13 +00:00 committed by Simon Horman
parent 8d68821ced
commit 9b55a05ebf
1 changed files with 17 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -48,7 +48,6 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* 1 core only at this point */
a53_0: cpu@0 { a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>; reg = <0>;
@ -58,6 +57,15 @@
enable-method = "psci"; enable-method = "psci";
}; };
a53_1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <1>;
device_type = "cpu";
power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-0 { L2_CA53: cache-controller-0 {
compatible = "cache"; compatible = "cache";
power-domains = <&sysc R8A774C0_PD_CA53_SCU>; power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
@ -82,8 +90,9 @@
pmu_a53 { pmu_a53 {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
interrupt-affinity = <&a53_0>; <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>;
}; };
psci { psci {
@ -604,7 +613,7 @@
<0x0 0xf1040000 0 0x20000>, <0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>; <0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>; clocks = <&cpg CPG_MOD 408>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@ -619,10 +628,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
}; };
/* External USB clocks - can be overridden by the board */ /* External USB clocks - can be overridden by the board */