drm/nouveau/falcon: add msgqueue interface
A message queue firmware implements a specific protocol allowing the host to send "commands" to a falcon, and the falcon to reply using "messages". This patch implements the common part of this protocol and defines the interface that the host can use. Due to the way the firmware is developped internally at NVIDIA (where kernel driver and firmware evolve in lockstep), firmwares taken at different points in time can have frustratingly subtle differences that must be taken into account. This code is architectured to make implementing such differences as easy as possible. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
0117b3369f
commit
9b536e9d52
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@ -0,0 +1,47 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVKM_CORE_MSGQUEUE_H
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#define __NVKM_CORE_MSGQUEUE_H
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#include <core/os.h>
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struct nvkm_falcon;
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struct nvkm_msgqueue;
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enum nvkm_secboot_falcon;
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/* Hopefully we will never have firmware arguments larger than that... */
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#define NVKM_MSGQUEUE_CMDLINE_SIZE 0x100
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int nvkm_msgqueue_new(u32, struct nvkm_falcon *, struct nvkm_msgqueue **);
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void nvkm_msgqueue_del(struct nvkm_msgqueue **);
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void nvkm_msgqueue_recv(struct nvkm_msgqueue *);
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int nvkm_msgqueue_reinit(struct nvkm_msgqueue *);
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/* useful if we run a NVIDIA-signed firmware */
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void nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue *, void *);
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/* interface to ACR unit running on falcon (NVIDIA signed firmware) */
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int nvkm_msgqueue_acr_boot_falcon(struct nvkm_msgqueue *,
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enum nvkm_secboot_falcon);
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#endif
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@ -1,2 +1,3 @@
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nvkm-y += nvkm/falcon/base.o
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nvkm-y += nvkm/falcon/v1.o
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nvkm-y += nvkm/falcon/msgqueue.o
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@ -0,0 +1,544 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "msgqueue.h"
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#include <engine/falcon.h>
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#include <subdev/secboot.h>
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#define HDR_SIZE sizeof(struct nvkm_msgqueue_hdr)
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#define QUEUE_ALIGNMENT 4
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/* max size of the messages we can receive */
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#define MSG_BUF_SIZE 128
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static int
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msg_queue_open(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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mutex_lock(&queue->mutex);
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queue->position = nvkm_falcon_rd32(falcon, queue->tail_reg);
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return 0;
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}
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static void
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msg_queue_close(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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bool commit)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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if (commit)
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nvkm_falcon_wr32(falcon, queue->tail_reg, queue->position);
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mutex_unlock(&queue->mutex);
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}
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static bool
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msg_queue_empty(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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u32 head, tail;
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head = nvkm_falcon_rd32(falcon, queue->head_reg);
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tail = nvkm_falcon_rd32(falcon, queue->tail_reg);
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return head == tail;
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}
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static int
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msg_queue_pop(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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void *data, u32 size)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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u32 head, tail, available;
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head = nvkm_falcon_rd32(falcon, queue->head_reg);
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/* has the buffer looped? */
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if (head < queue->position)
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queue->position = queue->offset;
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tail = queue->position;
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available = head - tail;
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if (available == 0) {
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nvkm_warn(subdev, "no message data available\n");
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return 0;
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}
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if (size > available) {
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nvkm_warn(subdev, "message data smaller than read request\n");
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size = available;
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}
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nvkm_falcon_read_dmem(priv->falcon, tail, size, 0, data);
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queue->position += ALIGN(size, QUEUE_ALIGNMENT);
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return size;
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}
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static int
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msg_queue_read(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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struct nvkm_msgqueue_hdr *hdr)
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{
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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int err;
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err = msg_queue_open(priv, queue);
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if (err) {
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nvkm_error(subdev, "fail to open queue %d\n", queue->index);
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return err;
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}
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if (msg_queue_empty(priv, queue)) {
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err = 0;
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goto close;
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}
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err = msg_queue_pop(priv, queue, hdr, HDR_SIZE);
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if (err >= 0 && err != HDR_SIZE)
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err = -EINVAL;
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if (err < 0) {
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nvkm_error(subdev, "failed to read message header: %d\n", err);
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goto close;
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}
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if (hdr->size > MSG_BUF_SIZE) {
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nvkm_error(subdev, "message too big (%d bytes)\n", hdr->size);
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err = -ENOSPC;
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goto close;
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}
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if (hdr->size > HDR_SIZE) {
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u32 read_size = hdr->size - HDR_SIZE;
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err = msg_queue_pop(priv, queue, (hdr + 1), read_size);
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if (err >= 0 && err != read_size)
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err = -EINVAL;
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if (err < 0) {
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nvkm_error(subdev, "failed to read message: %d\n", err);
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goto close;
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}
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}
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close:
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msg_queue_close(priv, queue, (err >= 0));
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return err;
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}
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static bool
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cmd_queue_has_room(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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u32 size, bool *rewind)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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u32 head, tail, free;
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size = ALIGN(size, QUEUE_ALIGNMENT);
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head = nvkm_falcon_rd32(falcon, queue->head_reg);
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tail = nvkm_falcon_rd32(falcon, queue->tail_reg);
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if (head >= tail) {
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free = queue->offset + queue->size - head;
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free -= HDR_SIZE;
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if (size > free) {
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*rewind = true;
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head = queue->offset;
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}
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}
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if (head < tail)
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free = tail - head - 1;
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return size <= free;
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}
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static int
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cmd_queue_push(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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void *data, u32 size)
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{
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nvkm_falcon_load_dmem(priv->falcon, data, queue->position, size, 0);
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queue->position += ALIGN(size, QUEUE_ALIGNMENT);
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return 0;
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}
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/* REWIND unit is always 0x00 */
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#define MSGQUEUE_UNIT_REWIND 0x00
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static void
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cmd_queue_rewind(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue)
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{
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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struct nvkm_msgqueue_hdr cmd;
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int err;
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cmd.unit_id = MSGQUEUE_UNIT_REWIND;
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cmd.size = sizeof(cmd);
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err = cmd_queue_push(priv, queue, &cmd, cmd.size);
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if (err)
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nvkm_error(subdev, "queue %d rewind failed\n", queue->index);
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else
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nvkm_error(subdev, "queue %d rewinded\n", queue->index);
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queue->position = queue->offset;
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}
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static int
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cmd_queue_open(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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u32 size)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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bool rewind = false;
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mutex_lock(&queue->mutex);
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if (!cmd_queue_has_room(priv, queue, size, &rewind)) {
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nvkm_error(subdev, "queue full\n");
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mutex_unlock(&queue->mutex);
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return -EAGAIN;
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}
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queue->position = nvkm_falcon_rd32(falcon, queue->head_reg);
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if (rewind)
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cmd_queue_rewind(priv, queue);
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return 0;
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}
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static void
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cmd_queue_close(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_queue *queue,
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bool commit)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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if (commit)
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nvkm_falcon_wr32(falcon, queue->head_reg, queue->position);
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mutex_unlock(&queue->mutex);
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}
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static int
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cmd_write(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *cmd,
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struct nvkm_msgqueue_queue *queue)
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{
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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static unsigned long timeout = ~0;
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unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
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int ret = -EAGAIN;
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bool commit = true;
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while (ret == -EAGAIN && time_before(jiffies, end_jiffies))
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ret = cmd_queue_open(priv, queue, cmd->size);
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if (ret) {
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nvkm_error(subdev, "pmu_queue_open_write failed\n");
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return ret;
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}
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ret = cmd_queue_push(priv, queue, cmd, cmd->size);
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if (ret) {
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nvkm_error(subdev, "pmu_queue_push failed\n");
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commit = false;
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}
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cmd_queue_close(priv, queue, commit);
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return ret;
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}
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static struct nvkm_msgqueue_seq *
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msgqueue_seq_acquire(struct nvkm_msgqueue *priv)
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{
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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struct nvkm_msgqueue_seq *seq;
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u32 index;
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mutex_lock(&priv->seq_lock);
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index = find_first_zero_bit(priv->seq_tbl, NVKM_MSGQUEUE_NUM_SEQUENCES);
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if (index >= NVKM_MSGQUEUE_NUM_SEQUENCES) {
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nvkm_error(subdev, "no free sequence available\n");
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mutex_unlock(&priv->seq_lock);
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return ERR_PTR(-EAGAIN);
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}
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set_bit(index, priv->seq_tbl);
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mutex_unlock(&priv->seq_lock);
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seq = &priv->seq[index];
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seq->state = SEQ_STATE_PENDING;
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return seq;
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}
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static void
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msgqueue_seq_release(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_seq *seq)
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{
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/* no need to acquire seq_lock since clear_bit is atomic */
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seq->state = SEQ_STATE_FREE;
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seq->callback = NULL;
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seq->completion = NULL;
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clear_bit(seq->id, priv->seq_tbl);
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}
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/* specifies that we want to know the command status in the answer message */
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#define CMD_FLAGS_STATUS BIT(0)
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/* specifies that we want an interrupt when the answer message is queued */
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#define CMD_FLAGS_INTR BIT(1)
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int
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nvkm_msgqueue_post(struct nvkm_msgqueue *priv, enum msgqueue_msg_priority prio,
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struct nvkm_msgqueue_hdr *cmd, nvkm_msgqueue_callback cb,
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struct completion *completion, bool wait_init)
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{
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struct nvkm_msgqueue_seq *seq;
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struct nvkm_msgqueue_queue *queue;
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int ret;
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if (wait_init && !wait_for_completion_timeout(&priv->init_done,
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msecs_to_jiffies(1000)))
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return -ETIMEDOUT;
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queue = priv->func->cmd_queue(priv, prio);
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if (IS_ERR(queue))
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return PTR_ERR(queue);
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seq = msgqueue_seq_acquire(priv);
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if (IS_ERR(seq))
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return PTR_ERR(seq);
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cmd->seq_id = seq->id;
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cmd->ctrl_flags = CMD_FLAGS_STATUS | CMD_FLAGS_INTR;
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seq->callback = cb;
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seq->state = SEQ_STATE_USED;
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seq->completion = completion;
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ret = cmd_write(priv, cmd, queue);
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if (ret) {
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seq->state = SEQ_STATE_PENDING;
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msgqueue_seq_release(priv, seq);
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}
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return ret;
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}
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static int
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msgqueue_msg_handle(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *hdr)
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{
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const struct nvkm_subdev *subdev = priv->falcon->owner;
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struct nvkm_msgqueue_seq *seq;
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seq = &priv->seq[hdr->seq_id];
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if (seq->state != SEQ_STATE_USED && seq->state != SEQ_STATE_CANCELLED) {
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nvkm_error(subdev, "msg for unknown sequence %d", seq->id);
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return -EINVAL;
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}
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if (seq->state == SEQ_STATE_USED) {
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if (seq->callback)
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seq->callback(priv, hdr);
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}
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if (seq->completion)
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complete(seq->completion);
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msgqueue_seq_release(priv, seq);
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return 0;
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}
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static int
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msgqueue_handle_init_msg(struct nvkm_msgqueue *priv,
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struct nvkm_msgqueue_hdr *hdr)
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{
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struct nvkm_falcon *falcon = priv->falcon;
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const struct nvkm_subdev *subdev = falcon->owner;
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u32 tail;
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u32 tail_reg;
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int ret;
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/*
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* Of course the message queue registers vary depending on the falcon
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* used...
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*/
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switch (falcon->owner->index) {
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case NVKM_SUBDEV_PMU:
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tail_reg = 0x4cc;
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break;
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default:
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nvkm_error(subdev, "falcon %s unsupported for msgqueue!\n",
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nvkm_subdev_name[falcon->owner->index]);
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return -EINVAL;
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}
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/*
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* Read the message - queues are not initialized yet so we cannot rely
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* on msg_queue_read()
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*/
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tail = nvkm_falcon_rd32(falcon, tail_reg);
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nvkm_falcon_read_dmem(falcon, tail, HDR_SIZE, 0, hdr);
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if (hdr->size > MSG_BUF_SIZE) {
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nvkm_error(subdev, "message too big (%d bytes)\n", hdr->size);
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return -ENOSPC;
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}
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nvkm_falcon_read_dmem(falcon, tail + HDR_SIZE, hdr->size - HDR_SIZE, 0,
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(hdr + 1));
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tail += ALIGN(hdr->size, QUEUE_ALIGNMENT);
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nvkm_falcon_wr32(falcon, tail_reg, tail);
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ret = priv->func->init_func->init_callback(priv, hdr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_msgqueue_process_msgs(struct nvkm_msgqueue *priv,
|
||||
struct nvkm_msgqueue_queue *queue)
|
||||
{
|
||||
/*
|
||||
* We are invoked from a worker thread, so normally we have plenty of
|
||||
* stack space to work with.
|
||||
*/
|
||||
u8 msg_buffer[MSG_BUF_SIZE];
|
||||
struct nvkm_msgqueue_hdr *hdr = (void *)msg_buffer;
|
||||
int ret;
|
||||
|
||||
/* the first message we receive must be the init message */
|
||||
if ((!priv->init_msg_received)) {
|
||||
ret = msgqueue_handle_init_msg(priv, hdr);
|
||||
if (!ret)
|
||||
priv->init_msg_received = true;
|
||||
} else {
|
||||
while (msg_queue_read(priv, queue, hdr) > 0)
|
||||
msgqueue_msg_handle(priv, hdr);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_msgqueue_write_cmdline(struct nvkm_msgqueue *queue, void *buf)
|
||||
{
|
||||
if (!queue || !queue->func || !queue->func->init_func)
|
||||
return;
|
||||
|
||||
queue->func->init_func->gen_cmdline(queue, buf);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_msgqueue_acr_boot_falcon(struct nvkm_msgqueue *queue, enum nvkm_secboot_falcon falcon)
|
||||
{
|
||||
if (!queue || !queue->func->acr_func || !queue->func->acr_func->boot_falcon)
|
||||
return -ENODEV;
|
||||
|
||||
return queue->func->acr_func->boot_falcon(queue, falcon);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_msgqueue_new(u32 version, struct nvkm_falcon *falcon, struct nvkm_msgqueue **queue)
|
||||
{
|
||||
const struct nvkm_subdev *subdev = falcon->owner;
|
||||
int ret = -EINVAL;
|
||||
|
||||
switch (version) {
|
||||
default:
|
||||
nvkm_error(subdev, "unhandled firmware version 0x%08x\n",
|
||||
version);
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret == 0) {
|
||||
nvkm_debug(subdev, "firmware version: 0x%08x\n", version);
|
||||
(*queue)->fw_version = version;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_msgqueue_del(struct nvkm_msgqueue **queue)
|
||||
{
|
||||
if (*queue) {
|
||||
(*queue)->func->dtor(*queue);
|
||||
*queue = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_msgqueue_recv(struct nvkm_msgqueue *queue)
|
||||
{
|
||||
if (!queue || !queue->func || !queue->func->recv) {
|
||||
const struct nvkm_subdev *subdev = queue->falcon->owner;
|
||||
|
||||
nvkm_warn(subdev,
|
||||
"cmdqueue recv function called while no firmware set!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
queue->func->recv(queue);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_msgqueue_reinit(struct nvkm_msgqueue *queue)
|
||||
{
|
||||
/* firmware not set yet... */
|
||||
if (!queue)
|
||||
return 0;
|
||||
|
||||
queue->init_msg_received = false;
|
||||
reinit_completion(&queue->init_done);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func *func,
|
||||
struct nvkm_falcon *falcon,
|
||||
struct nvkm_msgqueue *queue)
|
||||
{
|
||||
int i;
|
||||
|
||||
queue->func = func;
|
||||
queue->falcon = falcon;
|
||||
mutex_init(&queue->seq_lock);
|
||||
for (i = 0; i < NVKM_MSGQUEUE_NUM_SEQUENCES; i++)
|
||||
queue->seq[i].id = i;
|
||||
|
||||
init_completion(&queue->init_done);
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __NVKM_CORE_FALCON_MSGQUEUE_H
|
||||
#define __NVKM_CORE_FALCON_MSGQUEUE_H
|
||||
|
||||
#include <core/msgqueue.h>
|
||||
|
||||
/*
|
||||
* The struct nvkm_msgqueue (named so for lack of better candidate) manages
|
||||
* a firmware (typically, NVIDIA signed firmware) running under a given falcon.
|
||||
*
|
||||
* Such firmwares expect to receive commands (through one or several command
|
||||
* queues) and will reply to such command by sending messages (using one
|
||||
* message queue).
|
||||
*
|
||||
* Each firmware can support one or several units - ACR for managing secure
|
||||
* falcons, PMU for power management, etc. A unit can be seen as a class to
|
||||
* which command can be sent.
|
||||
*
|
||||
* One usage example would be to send a command to the SEC falcon to ask it to
|
||||
* reset a secure falcon. The SEC falcon will receive the command, process it,
|
||||
* and send a message to signal success or failure. Only when the corresponding
|
||||
* message is received can the requester assume the request has been processed.
|
||||
*
|
||||
* Since we expect many variations between the firmwares NVIDIA will release
|
||||
* across GPU generations, this library is built in a very modular way. Message
|
||||
* formats and queues details (such as number of usage) are left to
|
||||
* specializations of struct nvkm_msgqueue, while the functions in msgqueue.c
|
||||
* take care of posting commands and processing messages in a fashion that is
|
||||
* universal.
|
||||
*
|
||||
*/
|
||||
|
||||
enum msgqueue_msg_priority {
|
||||
MSGQUEUE_MSG_PRIORITY_HIGH,
|
||||
MSGQUEUE_MSG_PRIORITY_LOW,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_hdr - header for all commands/messages
|
||||
* @unit_id: id of firmware using receiving the command/sending the message
|
||||
* @size: total size of command/message
|
||||
* @ctrl_flags: type of command/message
|
||||
* @seq_id: used to match a message from its corresponding command
|
||||
*/
|
||||
struct nvkm_msgqueue_hdr {
|
||||
u8 unit_id;
|
||||
u8 size;
|
||||
u8 ctrl_flags;
|
||||
u8 seq_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_msg - base message.
|
||||
*
|
||||
* This is just a header and a message (or command) type. Useful when
|
||||
* building command-specific structures.
|
||||
*/
|
||||
struct nvkm_msgqueue_msg {
|
||||
struct nvkm_msgqueue_hdr hdr;
|
||||
u8 msg_type;
|
||||
};
|
||||
|
||||
struct nvkm_msgqueue;
|
||||
typedef void
|
||||
(*nvkm_msgqueue_callback)(struct nvkm_msgqueue *, struct nvkm_msgqueue_hdr *);
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_init_func - msgqueue functions related to initialization
|
||||
*
|
||||
* @gen_cmdline: build the commandline into a pre-allocated buffer
|
||||
* @init_callback: called to process the init message
|
||||
*/
|
||||
struct nvkm_msgqueue_init_func {
|
||||
void (*gen_cmdline)(struct nvkm_msgqueue *, void *);
|
||||
int (*init_callback)(struct nvkm_msgqueue *, struct nvkm_msgqueue_hdr *);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_acr_func - msgqueue functions related to ACR
|
||||
*
|
||||
* @boot_falcon: build and send the command to reset a given falcon
|
||||
*/
|
||||
struct nvkm_msgqueue_acr_func {
|
||||
int (*boot_falcon)(struct nvkm_msgqueue *, enum nvkm_secboot_falcon);
|
||||
};
|
||||
|
||||
struct nvkm_msgqueue_func {
|
||||
const struct nvkm_msgqueue_init_func *init_func;
|
||||
const struct nvkm_msgqueue_acr_func *acr_func;
|
||||
void (*dtor)(struct nvkm_msgqueue *);
|
||||
struct nvkm_msgqueue_queue *(*cmd_queue)(struct nvkm_msgqueue *,
|
||||
enum msgqueue_msg_priority);
|
||||
void (*recv)(struct nvkm_msgqueue *queue);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_queue - information about a command or message queue
|
||||
*
|
||||
* The number of queues is firmware-dependent. All queues must have their
|
||||
* information filled by the init message handler.
|
||||
*
|
||||
* @mutex_lock: to be acquired when the queue is being used
|
||||
* @index: physical queue index
|
||||
* @offset: DMEM offset where this queue begins
|
||||
* @size: size allocated to this queue in DMEM (in bytes)
|
||||
* @position: current write position
|
||||
* @head_reg: address of the HEAD register for this queue
|
||||
* @tail_reg: address of the TAIL register for this queue
|
||||
*/
|
||||
struct nvkm_msgqueue_queue {
|
||||
struct mutex mutex;
|
||||
u32 index;
|
||||
u32 offset;
|
||||
u32 size;
|
||||
u32 position;
|
||||
|
||||
u32 head_reg;
|
||||
u32 tail_reg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue_seq - keep track of ongoing commands
|
||||
*
|
||||
* Every time a command is sent, a sequence is assigned to it so the
|
||||
* corresponding message can be matched. Upon receiving the message, a callback
|
||||
* can be called and/or a completion signaled.
|
||||
*
|
||||
* @id: sequence ID
|
||||
* @state: current state
|
||||
* @callback: callback to call upon receiving matching message
|
||||
* @completion: completion to signal after callback is called
|
||||
*/
|
||||
struct nvkm_msgqueue_seq {
|
||||
u16 id;
|
||||
enum {
|
||||
SEQ_STATE_FREE = 0,
|
||||
SEQ_STATE_PENDING,
|
||||
SEQ_STATE_USED,
|
||||
SEQ_STATE_CANCELLED
|
||||
} state;
|
||||
nvkm_msgqueue_callback callback;
|
||||
struct completion *completion;
|
||||
};
|
||||
|
||||
/*
|
||||
* We can have an arbitrary number of sequences, but realistically we will
|
||||
* probably not use that much simultaneously.
|
||||
*/
|
||||
#define NVKM_MSGQUEUE_NUM_SEQUENCES 16
|
||||
|
||||
/**
|
||||
* struct nvkm_msgqueue - manage a command/message based FW on a falcon
|
||||
*
|
||||
* @falcon: falcon to be managed
|
||||
* @func: implementation of the firmware to use
|
||||
* @init_msg_received: whether the init message has already been received
|
||||
* @init_done: whether all init is complete and commands can be processed
|
||||
* @seq_lock: protects seq and seq_tbl
|
||||
* @seq: sequences to match commands and messages
|
||||
* @seq_tbl: bitmap of sequences currently in use
|
||||
*/
|
||||
struct nvkm_msgqueue {
|
||||
struct nvkm_falcon *falcon;
|
||||
const struct nvkm_msgqueue_func *func;
|
||||
u32 fw_version;
|
||||
bool init_msg_received;
|
||||
struct completion init_done;
|
||||
|
||||
struct mutex seq_lock;
|
||||
struct nvkm_msgqueue_seq seq[NVKM_MSGQUEUE_NUM_SEQUENCES];
|
||||
unsigned long seq_tbl[BITS_TO_LONGS(NVKM_MSGQUEUE_NUM_SEQUENCES)];
|
||||
};
|
||||
|
||||
void nvkm_msgqueue_ctor(const struct nvkm_msgqueue_func *, struct nvkm_falcon *,
|
||||
struct nvkm_msgqueue *);
|
||||
int nvkm_msgqueue_post(struct nvkm_msgqueue *, enum msgqueue_msg_priority,
|
||||
struct nvkm_msgqueue_hdr *, nvkm_msgqueue_callback,
|
||||
struct completion *, bool);
|
||||
void nvkm_msgqueue_process_msgs(struct nvkm_msgqueue *,
|
||||
struct nvkm_msgqueue_queue *);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue