sh_eth: factor out sh_eth_emac_interrupt()
The E-MAC interrupt (EESR.ECI) is not always caused by an error condition, so it really shouldn't be handled by sh_eth_error(). Factor out the E-MAC interrupt handler, sh_eth_emac_interrupt(), removing the ECI bit from the EESR's values throughout the driver... Update Cogent Embedded's copyright and clean up the whitespace in Renesas' copyright, while at it... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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1940f24076
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9b39f05ce8
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@ -3,7 +3,7 @@
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2006-2012 Nobuhiro Iwamatsu
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* Copyright (C) 2008-2014 Renesas Solutions Corp.
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* Copyright (C) 2013-2016 Cogent Embedded, Inc.
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* Copyright (C) 2013-2017 Cogent Embedded, Inc.
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* Copyright (C) 2014 Codethink Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -523,7 +523,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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EESR_TDE | EESR_ECI,
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EESR_TDE,
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.fdr_value = 0x0000070f,
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.no_psr = 1,
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@ -562,7 +562,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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EESR_TDE | EESR_ECI,
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EESR_TDE,
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.fdr_value = 0x0000070f,
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.apr = 1,
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@ -607,8 +607,7 @@ static struct sh_eth_cpu_data r8a777x_data = {
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.fdr_value = 0x00000f0f,
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.apr = 1,
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@ -630,8 +629,7 @@ static struct sh_eth_cpu_data r8a779x_data = {
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.fdr_value = 0x00000f0f,
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.trscer_err_mask = DESC_I_RINT8,
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@ -671,8 +669,7 @@ static struct sh_eth_cpu_data sh7724_data = {
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.apr = 1,
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.mpr = 1,
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@ -707,8 +704,7 @@ static struct sh_eth_cpu_data sh7757_data = {
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.tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
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.eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.irq_flags = IRQF_SHARED,
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.apr = 1,
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@ -776,7 +772,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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EESR_TDE | EESR_ECI,
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EESR_TDE,
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.fdr_value = 0x0000072f,
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.irq_flags = IRQF_SHARED,
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@ -807,7 +803,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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EESR_TDE | EESR_ECI,
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EESR_TDE,
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.apr = 1,
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.mpr = 1,
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@ -835,8 +831,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.tx_check = EESR_TC1 | EESR_FTC,
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.eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
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EESR_ECI,
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EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
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.apr = 1,
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.mpr = 1,
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@ -1526,24 +1521,21 @@ static void sh_eth_rcv_snd_enable(struct net_device *ndev)
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sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
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}
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/* error control function */
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static void sh_eth_error(struct net_device *ndev, u32 intr_status)
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/* E-MAC interrupt handler */
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static void sh_eth_emac_interrupt(struct net_device *ndev)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 felic_stat;
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u32 link_stat;
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u32 mask;
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if (intr_status & EESR_ECI) {
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felic_stat = sh_eth_read(ndev, ECSR) &
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sh_eth_read(ndev, ECSIPR);
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felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
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sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
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if (felic_stat & ECSR_ICD)
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ndev->stats.tx_carrier_errors++;
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if (felic_stat & ECSR_LCHNG) {
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/* Link Changed */
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if (mdp->cd->no_psr || mdp->no_ether_link)
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goto ignore_link;
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return;
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link_stat = sh_eth_read(ndev, PSR);
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if (mdp->ether_link_active_low)
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link_stat = ~link_stat;
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@ -1554,15 +1546,19 @@ static void sh_eth_error(struct net_device *ndev, u32 intr_status)
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sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
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/* clear int */
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sh_eth_modify(ndev, ECSR, 0, 0);
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sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
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DMAC_M_ECI);
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sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
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/* enable tx and rx */
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sh_eth_rcv_snd_enable(ndev);
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}
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}
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}
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}
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/* error control function */
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static void sh_eth_error(struct net_device *ndev, u32 intr_status)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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u32 mask;
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ignore_link:
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if (intr_status & EESR_TWB) {
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/* Unused write back interrupt */
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if (intr_status & EESR_TABT) { /* Transmit Abort int */
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@ -1645,12 +1641,14 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
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intr_status = sh_eth_read(ndev, EESR);
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/* Mask it with the interrupt mask, forcing ECI interrupt to be always
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* enabled since it's the one that comes thru regardless of the mask,
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* and we need to fully handle it in sh_eth_error() in order to quench
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* it as it doesn't get cleared by just writing 1 to the ECI bit...
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* and we need to fully handle it in sh_eth_emac_interrupt() in order
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* to quench it as it doesn't get cleared by just writing 1 to the ECI
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* bit...
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*/
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intr_enable = sh_eth_read(ndev, EESIPR);
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intr_status &= intr_enable | DMAC_M_ECI;
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if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
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if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
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cd->eesr_err_check))
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ret = IRQ_HANDLED;
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else
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goto out;
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@ -1682,6 +1680,10 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
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netif_wake_queue(ndev);
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}
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/* E-MAC interrupt */
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if (intr_status & EESR_ECI)
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sh_eth_emac_interrupt(ndev);
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if (intr_status & cd->eesr_err_check) {
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/* Clear error interrupts */
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sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
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@ -265,7 +265,7 @@ enum EESR_BIT {
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EESR_RTO)
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#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
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EESR_RDE | EESR_RFRMER | EESR_ADE | \
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EESR_TFE | EESR_TDE | EESR_ECI)
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EESR_TFE | EESR_TDE)
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/* EESIPR */
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enum DMAC_IM_BIT {
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